DIRECT CURRENT POWERED CLOCKLESS SUPERCONDUCTING LOGIC FAMILY USING DYNAMIC INTERNAL STATE

• US 20200136626A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rylov, Sergey
• Granted Patent: US 10,680,617 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03K 19/1952 with electro-magnetic coupling of the control current
• CPC Class Codes: H03K 3/38 by the use, as active elements, of superconductive devices

Abstract

Techniques regarding a DSFQ logic family are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a dynamic single flux quantum logic circuit that has a self-resetting internal state and can be powered by direct current. Further, the self-resetting internal state can be characterized by two time constants.

Claims

1. A system, comprising:

a dynamic single flux quantum logic circuit that has a self-resetting internal state and is powered by direct current, wherein the self-resetting internal state is characterized by two time constants, wherein the dynamic single flux quantum logic circuit is selected from a group consisting of an AND gate, an OR gate, a transparent latch, and a delay buffer.

2. The system of claim 1, wherein the two time constants are dictated by a storage element comprised within the dynamic single flux quantum logic circuit, and wherein the storage element is characterized by nonlinear leakage of magnetic flux.

3. The system of claim 2, wherein the nonlinear leakage of magnetic flux by the storage element reduces a reset duration of the self-resetting internal state, and wherein the reset duration is a period of time during which the dynamic single flux quantum logic circuit is in an intermediate state between an active state and a ground state.

4. The system of claim 3, wherein the active state has a dynamic hold time that lasts longer than the reset duration.

5. The system of claim 2, wherein the storage element comprises an inductor connected in series with a nonlinear magnetic flux leakage element.

6. The system of claim 2, wherein the storage element comprises a nonlinear magnetic flux leakage element that further comprises:

a first branch comprising a first Josephson junction arranged in series with a resistor; and

a second branch connected in parallel with the first branch and comprising a second Josephson junction.

7. The system of claim 6, wherein a first time constant of the two time constants is an intrinsic time constraint of Josephson junctions, and wherein a second time constant of the two time constants is defined by the resistor.

9. The system of claim 1, wherein the AND gate comprises a first dynamic storage loop and a second dynamic storage loop operatively coupled to an output Josephson junction that is biased by direct current, wherein the first dynamic storage loop is comprises a series connection of the nonlinear magnetic flux leakage element and a first storage inductor, and wherein the second dynamic storage loop comprises a series connection of a second nonlinear magnetic flux leakage element and a second storage inductor.

10. The system of claim 9, wherein the second nonlinear magnetic flux leakage element comprises:

a third branch comprising a third Josephson junction arranged in series with a second resistor; and

a fourth branch connected in parallel with the third branch and comprising a fourth Josephson junction.

11. The system of claim 9, wherein the first dynamic storage loop is driven by a first data input port, and wherein the second dynamic storage loop is driven by a second data input port.

12. The system of claim 1, wherein the OR gate comprises:

a dynamic storage loop between a bias source and a ground port, wherein the dynamic storage loop comprises a series connection of the nonlinear magnetic flux leakage element and a storage inductor; and

a confluence buffer arranged in series with a third Josephson junction at a first input port and a fourth Josephson junction at a second input port.

13. The system of claim 1, wherein the transparent latch comprises a dynamic storage loop and a static storage loop operatively coupled to an output Josephson junction that is biased by direct current, wherein the dynamic storage loop is driven by a clock input port and comprises a series connection of the nonlinear magnetic flux leakage element and a first storage inductor, and wherein the static storage loop is driven by a data input port and comprises a second storage inductor.

14. The system of claim 1, wherein the delay buffer comprises:

the nonlinear magnetic flux leakage element arranged between a storage inductor and a ground port; and

an output port arranged between the nonlinear magnetic flux leakage element and the storage inductor, wherein a direct current bias is applied to the output port.

8. (canceled)

15-20. -20. (canceled)