CIRCUIT AND METHOD FOR CONTROL OF COUNTER START TIME
1. An analog to digital conversion (ADC) circuit, comprising:
- a ramp circuit coupled to output a ramp signal, wherein the ramp signal is offset from a starting voltage by an offset voltage, and wherein the ramp signal ramps towards the starting voltage;
a counter circuit coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage; and
a comparator coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline, and in response to the ramp signal equaling the pixel signal voltage, stop the counter.
An analog to digital conversion (ADC) circuit includes a ramp circuit coupled to output a ramp signal, and the ramp signal is offset from a starting voltage by an offset voltage. The ramp signal ramps towards the starting voltage. A counter circuit is coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage, and a comparator is coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline. In response to the ramp signal equaling the pixel signal voltage, the comparator stops the counter.
- 1. An analog to digital conversion (ADC) circuit, comprising:
a ramp circuit coupled to output a ramp signal, wherein the ramp signal is offset from a starting voltage by an offset voltage, and wherein the ramp signal ramps towards the starting voltage; a counter circuit coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage; and a comparator coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline, and in response to the ramp signal equaling the pixel signal voltage, stop the counter.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- 11. A method of analog to digital conversion, comprising:
offsetting a ramp signal from a starting voltage by an offset voltage; ramping, with a ramp circuit, the ramp signal towards the starting voltage; starting a counter after the ramp signal returns to the starting voltage; comparing the ramp signal to a pixel signal voltage using a comparator coupled to the ramp circuit; and in response to the ramp signal equaling the pixel signal voltage, stopping the counter.
- View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
This disclosure relates generally to electronic devices, and in particular but not exclusively, relates to analog to digital converters.
Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as medical, automobile, and other applications. High dynamic range (HDR) image sensors have been required by many of those applications. Human eyes normally possess a dynamic range of up to about 100 dB. For automobile applications, an image sensor of more than 100 dB dynamic range may be necessary to deal with different driving conditions, such as driving through a dark tunnel into bright sunlight.
When image sensors are used, photo-generated electrons in each of the plurality of pixel cells are transferred from the photodiode to a floating diffusion for subsequent readout. The image signal on the floating diffusion is amplified by a source follower transistor. When a row select transistor is enabled, the amplified image signal is transferred to an output line, called a bitline, of the pixel cell.
The image signal on the bitline is normally fed into an analog to digital converter (ADC) to be converted to digital image signal. A ramp type ADC is often used in association with image sensors.
Non-limiting and non-exhaustive examples of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.
Examples of an apparatus and method for control of a counter start time are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.
Reference throughout this specification to “one example” or “one embodiment” means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases “in one example” or “in one embodiment” in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.
As shown in
The system starts the counter at a later time (see e.g., “counter 2”) to account for the offset voltage, in accordance with the teachings of the present disclosure. This saves an appreciable amount of power. Both the ramp reference signal (Vref) and ramp image signal (“Vsignal”) from the pixel may be delayed for the same amount of time, so the delay of count_en won'"'"'t affect the final readout data. Thus in one example, for 300DN delayed counter_en, the system saves about ⅓ counter power in the dark condition (e.g., when the image sensor is not receiving light).
As stated, the power consumption of a counter is almost proportional to its final number of counts. In a dark condition, the power consumption of image data follows a Gaussian (bell-curve-like) distribution. When plotted as a histogram, the output data will have a median count “Mediandark” (i.e., the value at the center of the bell curve), and a minimum value of “Mindark” (i.e., the value at the start of the bell curve). The power consumption of the counter is proportional to Mediandark. Here, the system starts counting at a later time, so that Mindark is almost 0. The power consumption of the new timing is proportional to (Mediandark−Mindark). And compared to previous timing (e.g., “counter 1”), the average power saving ratio is (Mindark)/(Mediandark).
As an example, when the median is 390, and the min is 300, the system here saves 76% counting power for the first ramp. For an image average around 512, the system here saves about 300/(390+512)=33% counting power for the second ramp. For digital correlated double sampling (CDS) operation, the average power savings of both count reference and count signal is: (300+300)/(390+390+512)=46.4%. Thus, if digital power were ˜50% of total power and counter power were ˜20% of digital power, then in the dark condition, the system here could save 4.6% of total power.
As shown, the techniques disclosed herein may be used with correlated double sampling so that the counter starts counting later for both the black level reference voltage (e.g., “Vref” in
As stated circuit diagram 201A may generate the count_en and ramp_en signals in
As shown, instead of using a delay unit (e.g., clocked delay unit 207
In one example, a histogram algorithm block on-chip may be used to produce the delay for count_en (which may be calculated dynamically) instead of using one-time-programmable memory to store the register values based on chip tests. Extra optical black rows (including black pixels—e.g., pixels where light is blocked from reaching the pixel) are used for black level calibration (BLC), and the data of these extra rows are used to determine the minimum count. In some examples, the system may only apply a delayed count_en for normal BLC and image rows. One benefit of this approach is that count_en can be adjusted dynamically, but it also consumes extra power.
In one example, after each image sensor photodiode/pixel in pixel array 305 has acquired its image data or image charge, the image data is readout by readout circuitry 311 and then transferred to function logic 315. In various examples, readout circuitry 311 may include amplification circuitry, analog to digital conversion 317 circuitry (e.g., analog to digital conversion circuitry from
In one example, control circuitry 321 is coupled to pixel array 305 to control operation of the plurality of photodiodes in pixel array 305. For example, control circuitry 321 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within pixel array 305 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows. In another example, image acquisition is synchronized with lighting effects such as a flash.
As shown, the image sensor may include one or more rows of black pixels (e.g., pixels that are prevented from receiving light by virtue of a metal shield or the like), and a length of a delay between starting the ramp signal and starting the counter may be determined dynamically by reading out a black pixel voltage from the one or more black pixels.
In one example, imaging system 300 may be included in an automobile or the like. Additionally, imaging system 300 may be coupled to other pieces of hardware such as a processor (general purpose or otherwise), memory elements, output (USB port, wireless transmitter, HDMI port, etc.), lighting/flash, electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and/or display. Other pieces of hardware may deliver instructions to imaging system 300, extract image data from imaging system 300, or manipulate image data supplied by imaging system 300.
Block 401 illustrates offsetting a ramp signal from a starting voltage by an offset voltage. As stated above, the ramp signal is substantially linear but there may be a nonlinear portion at a beginning of the ramp signal (due to comparator and ramp delay). Accordingly, the offset voltage is of a magnitude so that the ramp signal becomes substantially linear prior to the ramp signal returning to the starting voltage.
Block 403 illustrates ramping, with a ramp circuit, the ramp signal towards the starting voltage. This may include ramping in either positive or negative directions.
Block 405 shows starting a counter after the ramp signal returns to the starting voltage. In one example, the length of the delay between starting ramping the ramp signal and starting the counter is programmed into one-time-programmable memory (e.g., static memory). In other examples, the length of the delay between starting ramping the ramp signal and starting the counter is determined dynamically by reading out a black pixel voltage from one or more black pixels. In this example, the black pixel voltage is used to form a histogram of black pixel voltage data, and the histogram of black pixel voltage data is used (e.g., by taking the median, average, high, or low value of the histogram) to dynamically determine the length of the delay.
Block 407 depicts comparing the ramp signal to a pixel signal voltage using a comparator coupled to the ramp circuit. The first pixel signal voltage read from the bitline may be a black level reference voltage (e.g., the voltage read out of a pixel that has been reset and has not generated image charge).
Block 409 shows in response to the ramp signal equaling the pixel signal voltage, stopping the counter. Thus, the system has established a digital value for the pixel signal voltage.
As shown, method 400 repeats itself to read out the pixel signal voltage for a second time (i.e., reading out a second pixel signal voltage; see e.g., second ramp of
Once the method 400 repeats itself, the first pixel signal voltage (e.g., the black level reference voltage) may be subtracted from the second pixel signal voltage (e.g., the image signal voltage) to perform black level correction. As shown in
The above description of illustrated examples of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.