CIRCUIT AND METHOD FOR CONTROL OF COUNTER START TIME

• US 20200136630A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Wang, Rui, Yang, Yu-Shen, Chen, Shan, Qu, Min
• Granted Patent: US 11,128,307 B2
• Time in Patent Office: Days
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/1295 Clamping, i.e. adjusting the DC level of the input signal to a predetermined value
• CPC Class Codes: H03M 1/56 Input signal compared with linear ramp
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/633 by using optical black pixels
• CPC Class Codes: H04N 25/673 by using reference sources
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/7795 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An analog to digital conversion (ADC) circuit includes a ramp circuit coupled to output a ramp signal, and the ramp signal is offset from a starting voltage by an offset voltage. The ramp signal ramps towards the starting voltage. A counter circuit is coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage, and a comparator is coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline. In response to the ramp signal equaling the pixel signal voltage, the comparator stops the counter.

Claims

1. An analog to digital conversion (ADC) circuit, comprising:

a ramp circuit coupled to output a ramp signal, wherein the ramp signal is offset from a starting voltage by an offset voltage, and wherein the ramp signal ramps towards the starting voltage;

a counter circuit coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage; and

a comparator coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline, and in response to the ramp signal equaling the pixel signal voltage, stop the counter.

2. The ADC circuit of claim 1, wherein the pixel signal voltage is a black level reference voltage.

3. The ADC circuit of claim 2, wherein:

a second ramp signal, output from the ramp circuit, is offset from the starting voltage by the offset voltage, and wherein the second ramp signal ramps towards the starting voltage;

the counter circuit starts counting when the second ramp signal returns to the starting voltage; and

the comparator compares the second ramp signal to a second pixel signal voltage on the bitline, and in response to the second ramp signal equaling the second pixel signal voltage, the comparator stops the counter.

4. The ADC circuit of claim 3, wherein the second pixel signal voltage is an image signal voltage, and wherein the second pixel signal voltage has a greater absolute magnitude than the pixel signal voltage and occurs after the pixel signal voltage.

5. The ADC circuit of claim 1, further comprising circuitry coupled to supply a length of a delay between starting the ramp signal and starting the counter.

6. The ADC circuit of claim 5, wherein the circuitry includes at least one of:

a clock delay unit where the length of the delay is stored in one-time-programmable memory;

or

one or more dividers coupled to provide the length of the delay.

7. The ADC circuit of claim 1, wherein the bitline is coupled to individual pixels in an image sensor.

8. The ADC circuit of claim 1, wherein the image sensor includes one or more black pixels, and wherein a length of a delay between starting the ramp signal and starting the counter is determined dynamically by reading out a black pixel voltage from the one or more black pixels.

9. The ADC circuit of claim 8, wherein the black pixel voltage is used to form a histogram of black pixel voltage data, and wherein the histogram of black pixel voltage data is used to dynamically determine the length of the delay.

10. The ADC circuit of claim 1, wherein the ramp signal is substantially linear with a nonlinear portion at a beginning of the ramp signal, and wherein the offset voltage is of a magnitude so the ramp signal becomes substantially linear prior to the ramp signal returning to the starting voltage.

11. A method of analog to digital conversion, comprising:

offsetting a ramp signal from a starting voltage by an offset voltage;

ramping, with a ramp circuit, the ramp signal towards the starting voltage;

starting a counter after the ramp signal returns to the starting voltage;

comparing the ramp signal to a pixel signal voltage using a comparator coupled to the ramp circuit; and

in response to the ramp signal equaling the pixel signal voltage, stopping the counter.

12. The method of claim 11, wherein the pixel signal voltage is a black level reference voltage.

13. The method of claim 12, further comprising:

offsetting a second ramp signal from the starting voltage by the offset voltage;

ramping, with the ramp circuit, the second ramp signal towards the starting voltage;

starting the counter when the second ramp signal returns to the starting voltage;

comparing the second ramp signal to a second pixel signal voltage using the comparator; and

in response to the second ramp signal equaling the second pixel signal voltage, stopping the counter.

14. The method of claim 13, wherein the second pixel signal voltage is an image signal voltage, wherein the second pixel signal voltage has a greater absolute magnitude than the pixel signal voltage and occurs after the pixel signal voltage.

15. The method of claim 11, further comprising subtracting the pixel signal voltage from the second pixel signal voltage to perform black level correction.

16. The method of claim 11, wherein a length of a delay between starting ramping the ramp signal and starting the counter is programmed into one-time-programmable memory.

17. The method of claim 11, wherein a length of a delay between starting ramping the ramp signal and starting the counter is determined dynamically by reading out a black pixel voltage from one or more black pixels.

18. The method of claim 17, wherein the black pixel voltage is used to form a histogram of black pixel voltage data, and wherein the histogram of black pixel voltage data is used to dynamically determine the length of the delay.

19. The method of claim 11, wherein the ramp signal is substantially linear with a nonlinear portion at a beginning of the ramp signal, and wherein the offset voltage is of a magnitude so the ramp signal becomes substantially linear prior to the ramp signal returning to the starting voltage.

20. The method of claim 11, wherein the comparator is coupled to a bitline of an image sensor to compare the ramp signal to the pixel signal voltage.