APPARATUS, CIRCUITS AND METHODS FOR CALIBRATING A TIME TO DIGITAL CONVERTER

• US 20200136632A1
• Filed: 09/18/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIN, Yu-Tso
• Granted Patent: US 10,763,876 B2
• Time in Patent Office: Days
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03M 1/1009 Calibration

Abstract

Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.

Claims

1. A circuit for calibrating a time to digital converter (TDC), comprising:

a multi-bit delay circuit configured for delaying a clock signal by a total delay time;

a counter configured for counting rising edges of the clock signal within the total delay time to generate a counted output; and

a register configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.

2. The circuit of claim 1, wherein the TDC is configured for converting the clock signal into a digital output.

3. The circuit of claim 1, wherein:

the multi-bit delay circuit comprises a plurality of delay cells connected in series to one another; and

the total delay time of the multi-bit delay circuit is variable according to active and inactive delay cells of the plurality of delay cells based on a register value of the register.

4. The circuit of claim 3, further comprising:

a switch that is coupled to the plurality of delay cells and configured for selecting at least one of the plurality of delay cells to activate based on the register value of the register.

5. The circuit of claim 3, further comprising:

a plurality of switches each of which is coupled to a respective one of the plurality of delay cells and configured for activating or deactivating the delay cell based on the register value of the register.

6. The circuit of claim 1, further comprising a decision logic circuit coupled to the counter and configured for:

determining whether the counted output is larger than or equal to a threshold to generate a determination result; and

providing the determination result to the register.

7. The circuit of claim 6, wherein the threshold is two and represents a condition that the total delay time covers at least one period of the clock signal.

8. The circuit of claim 1, further comprising a first logic gate configured for:

gating the clock signal based on a reference signal to generate a step-up signal, wherein the step-up signal is provided to the multi-bit delay circuit as an input.

9. The circuit of claim 8, further comprising a second logic gate configured for:

receiving the step-up signal and a step-down signal that is an output of the multi-bit delay circuit; and

generating a pulse signal based on the step-up signal and the step-down signal, wherein the pulse signal has a pulse width representing the total delay time.

10. The circuit of claim 9, further comprising a third logic gate configured for:

gating the clock signal based on the pulse signal to generate an input to the counter.

11. An apparatus for calibrating a time to digital converter (TDC), comprising:

a multi-bit delay circuit configured for delaying a clock signal by a total delay time;

a counter configured for comparing the total delay time with one period of the clock signal to generate a comparison output; and

a register configured for controlling the total delay time of the multi-bit delay circuit based on the comparison output.

12. The apparatus of claim 11, wherein the register is further configured for:

initializing, for calibrating the TDC, a register value of the register to enable the multi-bit delay circuit to have a minimum total delay time.

13. The apparatus of claim 12, wherein the register is further configured for:

based on a comparison output that the total delay time is not larger than one period of the clock signal, modifying the register value to enable the multi-bit delay circuit to have a larger total delay time; and

based on a comparison output that the total delay time is larger than one period of the clock signal, fixing the register value to fix the total delay time of the multi-bit delay circuit.

14. The apparatus of claim 13, wherein the register is further configured for:

adjusting the register value based on a change of at least one TDC condition.

15. A method for calibrating a time to digital converter (TDC), comprising:

passing a first signal through at least one of a plurality of delay cells of the TDC that is configured to determine a phase difference between the first signal and a second signal;

measuring a total delay time for the first signal to pass through the at least one delay cell;

determining that whether the total delay time is larger than one period of the first signal to generate a determination result; and

calibrating the TDC based on the determination result.

16. The method of claim 15, wherein:

the first signal is a local oscillator clock signal;

the second signal is a frequency reference signal; and

the period of the first signal is configured by a digitally controlled oscillator (DCO) associated with the TDC.

17. The method of claim 15, further comprising:

initializing a delay resolution setup of the TDC with a minimum delay time.

18. The method of claim 17, wherein calibrating the TDC comprises:

based on a determination that the total delay time is not larger than one period of the first signal, selecting a larger delay time for the delay resolution setup of the TDC; and

based on a determination that the total delay time is larger than one period of the first signal, fixing the delay resolution setup of the TDC.

19. The method of claim 18, wherein selecting a larger delay time for the delay resolution setup of the TDC comprises:

activating one additional delay cell from the plurality of delay cells for the first signal to pass.

20. The method of claim 15, further comprising:

monitoring the TDC to detect a change of at least one TDC condition;

determining, based on the detected change, that whether the total delay time is larger than one period of the first signal to generate an updated determination result; and

determining whether to re-calibrate the TDC based on the updated determination result.