ANALOG-TO-DIGITAL CONVERTER CONTROLLERS INCLUDING CONFIGURABLE CONTEXTS

• US 20200136635A1
• Filed: 12/31/2019
• Published: 04/30/2020
• Est. Priority Date: 10/16/2018
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Senapati, Ashish, Kilzer, Kevin, Pulipaka, Prashanth
• Granted Patent: US 11,101,812 B2
• Time in Patent Office: Days
• CPC Class Codes: H03M 1/004 Reconfigurable analogue/digital or digital/analogue converters H03M1/02 takes precedence
• CPC Class Codes: H03M 1/1205 Multiplexed conversion systems
• CPC Class Codes: H03M 1/1225 using time-division multiplexing

Abstract

Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of contexts configured for coupling to an ADC, wherein each context having at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence based on one or more configurable parameters of one or more contexts of the number of contexts. Methods of performing an analog-to-digital (A/D) conversion sequence, and methods of configuring a number of contexts for an analog-to-digital converter (ADC) controller, are also disclosed.

Claims

1. A method of configuring a number of contexts for an analog-to-digital converter (ADC) controller, comprising:

receiving a selection of a first context of a number of contexts, each context of the number of contexts including a number of registers;

receiving at least one parameter for the first context;

configuring the first context with the at least one parameter for the first context;

storing the first context as a first configured context of the ADC controller;

receiving a selection of at least one additional context of the number of contexts;

receiving at least one parameter for the at least one additional context;

configuring the at least one additional context with the at least one parameter for the at least one additional context; and

storing the at least one additional context as at least one additional configured context of the ADC controller.

2. The method of claim 1, further comprising:

displaying a set of special function registers of a number of registers for the first context in response to the selection of the first context; and

displaying a set of special function registers of a number of registers for the at least one additional context in response to the selection of the at least one additional context.

3. The method of claim 1, wherein the receiving the at least one parameter for the first context comprises receiving at least one of a sequence enable parameter and an interrupt parameter for the first context.

4. The method of claim 1, wherein the receiving the selection of the first context comprises receiving, via at least one interface, the selection of the first context via a context selection register displayed via the at least one interface.

5. The method of claim 1, further comprising selecting an input channel for the first context in response to receipt of the selection of the first context.

6. The method of claim 1, wherein the receiving the at least one parameter for the first context comprises receiving, via at least one interface, at least one of a sequence enable parameter via a channel sequence control register displayed via the at least one interface.

7. An analog-to-digital converter (ADC) controller, the ADC controller comprising:

a number of contexts configured for coupling to an ADC, each context having at least one register for storing at least one configurable parameter; and

a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence based on one or more configurable parameters of one or more contexts of the number of contexts.

8. The ADC controller of claim 7, wherein one configurable parameter of the one or more configurable parameters indicates whether the context is to be included in the programmed conversion sequence.

9. The ADC controller of claim 8, wherein the one configurable parameter that indicates whether or not the context is to be included in the programmed conversion sequence comprises a sequence enable bit.

10. The ADC controller of claim 7, wherein one configurable parameter of the at least one configurable parameter of each context comprises an interrupt parameter.

11. The ADC controller of claim 7, further comprising a context selector operatively coupled to the sequencer and configured to select a context of the number of contexts based on the programmed conversion sequence.

12. The ADC controller of claim 7, further comprising a peripheral bus operatively coupled to each of the number of contexts and the sequencer.

13. The ADC controller of claim 12, wherein each context is configured to receive a signal via the peripheral bus for configuring the at least one configurable parameter.

14. The ADC controller of claim 7, further comprising an input channel selector operatively coupled between the number of contexts and a number of input channels, the input channel selector configured to select an input channel of the number of input channels based on a signal from at least one of the number of contexts.

15. A method of performing an analog-to-digital (A/D) conversion sequence, the method comprising:

determining if a continuous operation bit of a first context of a number of contexts is asserted;

determining if a sequence enable bit of the first context is asserted;

in response to determining that the continuous operation bit of the first context is not asserted and the sequence enable bit of the first context is asserted, selecting a second context of the number of contexts; and

converting an input signal of an input channel associated with the second context to a digital signal.

16. The method of claim 15, further comprising:

determining if a continuous operation bit of the second context is asserted;

determining if a sequence enable bit of the second context is asserted;

in response to determining that the continuous operation bit of the second context is not asserted and the sequence enable bit of the second context is asserted, selecting a third context of the number of contexts; and

converting an input signal of an input channel associated with the third context to a digital signal.

17. The method of claim 15, further comprising:

determining if an interrupt flag for the first context has been triggered;

in response to determining that the interrupt flag for the first context has been triggered, determining if a stop on interrupt bit of the first context is asserted; and

in response to determining that the stop on interrupt bit of the first context is not asserted, converting an input signal of an input channel associated with the first context to a digital signal.

18. The method of claim 15, further comprising in response to determining that either the continuous operation bit of the first context is asserted or the sequence enable bit of the first context is not asserted, clearing an A/D conversion status bit of the first context.

19. The method of claim 15, further comprising detecting a trigger prior to converting a input signal of an input channel.

20. The method of claim 15, further comprising asserting an analog-to-digital (A/D) conversion status bit prior to converting an input signal of an input channel.