NOISE SHAPING IN A DIGITAL-TO-ANALOG CONVERTOR

• US 20200136638A1
• Filed: 10/30/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: HALDER, Tanmay, KANNAN, Anand
• Granted Patent: US 10,892,770 B2
• Time in Patent Office: Days
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00
• CPC Class Codes: H03M 1/066 by continuously permuting the elements used, i.e. dynamic element matching
• CPC Class Codes: H03M 1/08 of noise H03M1/0617 takes precedence
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/124 Sampling or signal conditioning arrangements specially adapted for A/D converters
• CPC Class Codes: H03M 1/442 using switched capacitors
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 3/30 Delta-sigma modulation
• CPC Class Codes: H03M 3/338 by permutation in the time domain, e.g. dynamic element matching in multiple bit sub-converters H03M1/066
• CPC Class Codes: H03M 3/344 by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
• CPC Class Codes: H03M 3/464 Details of the digital/analogue conversion in the feedback path
• CPC Class Codes: H03M 3/502 Details of the final digital/analogue conversion following the digital delta-sigma modulation
• CPC Class Codes: H03M 3/508 Details relating to the interpolation process

Abstract

Systems and methods are disclosed for a signal convertor comprising a resistor or current source coupled to a positive virtual ground node and a negative virtual ground node, wherein the resistor or current source is configured to switch from the positive virtual ground node (VGP) to the negative virtual ground node (VGN), wherein the switching of the resistor or current source results in a shaping of the low frequency noise from the resistor.

Claims

1. A method for shaping low frequency noise comprising:

converting a binary input to a thermometric code;

extracting signal information from the thermometric code;

decimating the signal information;

converting the signal information into a lower bit-count signal;

upsampling the lower bit-count signal;

applying mismatch shaping on a plurality of unit elements in the lower bit-count signal at a first DAC; and

outputting from the first DAC a signal component of the lower bit-count signal.

2. The method of claim 1, further comprising implementing the decimation ratio using a clock division value, R.

3. The method of claim 2, further comprising dynamically controlling the clock division value R based on an input code associated with the binary input.

4. The method of claim 1, further comprising obtaining an input code for a second DAC.

5. The method of claim 4, further comprising matching the shape of a mismatch error between a plurality of unit elements in the lower bit-count signal for the second DAC.

6. The method of claim 4, further comprising outputting from the second DAC a frequency component of the lower bit-count signal at a full rate.

7. The method of claim 1, further comprising using a low-pass filter to extract signal information from the thermometric code.

8. The method of claim 1, further comprising using a digital delta-sigma to convert the signal information into the lower bit-count signal.

9. The method of claim 2, further comprising using a frequency for the mismatch shaping that is derived from an input clock using the decimation ratio calculated by:

R=floor(ϕ

_DAC1/f_{noise_low}), wherein ϕ

_DAC1 represents the frequency of the input clock used by a switching controller and R has a minimum value.

10. A signal convertor, comprising:

a first resistor;

a first transistor;

a second transistor coupled to the first transistor and to the first resistor, the first transistor coupled to a positive virtual ground node and the second transistor coupled to a negative virtual ground node;

an element selection logic module coupled to the first and second transistors, the element selection module configured to switch a binary input from the positive virtual ground node (VGP) to the negative virtual ground node (VGN) through;

conversion of the binary input to a thermometric code;

extraction of signal information from the thermometric code;

decimation of the signal information;

conversion of the signal information into a lower bit-count signal;

upsampling of the lower bit-count signal;

application of mismatch shaping on a plurality of unit elements in the lower bit-count signal at a first digital-to-analog convertor (DAC); and

cause the first DAC to output a signal component of the lower bit-count signal.

11. The signal convertor of claim 10, wherein the decimation ratio is uses a clock division value, R.

12. The signal convertor of claim 11, wherein the element selection logic module is configured to dynamically control the clock division value R based on an input code associated with the binary input.

13. The signal convertor of claim 10, wherein the element selection logic module is further configured to obtain an input code for a second DAC.

14. The signal convertor of claim 13, wherein the element selection logic module is further configured to match the shape of a mismatch error between a plurality of unit elements and a low frequency noise in the lower bit-count signal for the second DAC.

15. The signal convertor of claim 13, wherein the first and second element selection logic module is further configured to cause an output from the second DAC of a frequency component of the lower bit-count signal at a full rate.

16. The signal convertor of claim 10, further comprising a low-pass filter, wherein the low pass filter is configured to extract signal information from the thermometric code.

17. The signal convertor of claim 10, further comprising a digital delta-sigma modulator coupled to the first and second transistors, wherein said digital delta-sigma modulator is configured to convert the signal information into the lower bit-count signal.

18. The signal convertor of claim 11, wherein the mismatch shaping uses a frequency that is derived from an input clock using the decimation ratio calculated by:

R=floor(ϕ

_DAC1/f_{noise_low}), wherein ϕ

_DAC1 represents the frequency of the input clock used by a switching controller and R has a minimum value.

19. A signal convertor comprising:

a digital-to-analog convertor comprised of a plurality of unit elements, wherein each of the unit elements comprises;

a first resistor;

a second resistor;

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor;

wherein

the first transistor is coupled to the first resistor at a virtual positive ground node and the second transistor coupled to the first resistor at a virtual negative ground node; and

the third transistor is coupled to the second resistor at the virtual positive ground node and the fourth transistor is coupled to the second resistor at the virtual negative ground node.

20. The signal convertor of claim 19, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are configured to switch an input from the virtual negative ground node to the virtual positive ground node.