Low Distortion Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) and Associated Methods
First Claim
1. An analog-to-digital converter (ADC) device comprising:
- a successive approximation register (SAR) configured to generate a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage;
a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal,wherein the DAC includes;
one or more first capacitors; and
a plurality of second capacitors coupled to the reference voltage, wherein the plurality of second capacitors are associated with the plurality of less significant bits.
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Accused Products
Abstract
An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage Vref=N*VDD, where N<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a supply (VDD), and one or more first capacitors also coupled to a supply (VDD) and associated with at least the MSB, and a plurality of second capacitors coupled to a reference (Vref), where Vref=N*VDD, where N<1, wherein the first capacitor having a capacitive value that is equal to (1−N) times the total capacitance of a parallel combination of the one or more first capacitors, the second capacitors associated with less significant bits, and an input voltage line carrying an input voltage (VIN) signal as the second input to the comparator.
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Citations
20 Claims
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1. An analog-to-digital converter (ADC) device comprising:
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a successive approximation register (SAR) configured to generate a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage; a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, wherein the DAC includes; one or more first capacitors; and a plurality of second capacitors coupled to the reference voltage, wherein the plurality of second capacitors are associated with the plurality of less significant bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for performing an analog-to-digital conversion, the method comprising:
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supplying an output of a comparator to an input of a successive approximation register (SAR) to generate based thereon a parallel digital output having a most significant bit (MSB), and a plurality of less significant bits; supplying the parallel digital output to a digital-to-analog converter (DAC) to generate based thereon an internal analog signal, wherein the DAC includes a first capacitor, a plurality of second capacitors, and a plurality of third capacitors, wherein the first capacitor is coupled between a first line carrying a first voltage and a second line carrying a second voltage, wherein the plurality of second capacitors is each switchable coupled between the first line and the second line and having respectively a value less than the first voltage, wherein the plurality of third capacitors is associated with the less significant bits and respectively switchably coupled between the first line and a third line carrying the third voltage. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A digital-to-analog converter (DAC), comprising:
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a first capacitor and a plurality of second capacitors, the first capacitor being coupled to a first line and a second line, and the plurality of second capacitors being coupled to the second line and to a first node switchably coupled by a first switch to a third line carrying a reference voltage, and wherein the first capacitor is not connected or switchably adapted to connect to the third line, wherein the first line carries a first voltage greater than the reference voltage, and wherein a successive approximation register (SAR) controls the first switch. - View Dependent Claims (18, 19, 20)
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Specification