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Low Distortion Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) and Associated Methods

  • US 20200136640A1
  • Filed: 12/10/2019
  • Published: 04/30/2020
  • Est. Priority Date: 09/28/2017
  • Status: Active Grant
First Claim
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1. An analog-to-digital converter (ADC) device comprising:

  • a successive approximation register (SAR) configured to generate a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage;

    a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal,wherein the DAC includes;

    one or more first capacitors; and

    a plurality of second capacitors coupled to the reference voltage, wherein the plurality of second capacitors are associated with the plurality of less significant bits.

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