Data Compressor Logic Circuit
First Claim
1. A compressor, comprising:
- first, second, and third logic gates each having respective first and second input terminals and an output terminal, wherein the first, second, and third logic gates are configured to output respective first, second, and third partial product bits at the respective output terminals;
a first circuit having first and second input terminals electrically coupled to the respective output terminals of the first and second logic gates, wherein the first circuit is configured to perform an XOR or XNOR logic operation on the first partial product bit or the second partial product bit to generate a resultant respective XOR or XNOR logic operation bit corresponding to one or more select signals; and
a first multiplexer having;
a first multiplexer select input terminal electrically coupled to the first circuit, anda first multiplexer output terminal,wherein the first multiplexer is configured to select a carry-out bit from among at least the first partial product bit and a third partial product bit based on the one or more select signals received at the first multiplexer select input terminal.
1 Assignment
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Accused Products
Abstract
A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.
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Citations
25 Claims
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1. A compressor, comprising:
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first, second, and third logic gates each having respective first and second input terminals and an output terminal, wherein the first, second, and third logic gates are configured to output respective first, second, and third partial product bits at the respective output terminals; a first circuit having first and second input terminals electrically coupled to the respective output terminals of the first and second logic gates, wherein the first circuit is configured to perform an XOR or XNOR logic operation on the first partial product bit or the second partial product bit to generate a resultant respective XOR or XNOR logic operation bit corresponding to one or more select signals; and a first multiplexer having; a first multiplexer select input terminal electrically coupled to the first circuit, and a first multiplexer output terminal, wherein the first multiplexer is configured to select a carry-out bit from among at least the first partial product bit and a third partial product bit based on the one or more select signals received at the first multiplexer select input terminal. - View Dependent Claims (2, 5, 6, 7)
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3. (canceled)
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4. (canceled)
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8. A method, comprising:
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receiving a first multiplicand bit and a first multiplier bit; performing, with a first NAND circuit, a logic NAND operation on the first multiplicand bit and the first multiplier bit, to generate a first output bit; receiving a second multiplicand bit and a second multiplier bit; performing, with a second NAND circuit, a logic NAND operation on the second multiplicand bit and the second multiplier bit, to generate a second output bit; performing a logic XOR operation with the first and second output bits to generate a first select signal; receiving a third multiplicand bit and a third multiplier bit; performing, with a third NAND circuit, a logic NAND operation on the third multiplicand bit and the third multiplier bit, to generate a third output bit; and selecting, at the multiplexer, a carry-out bit from among the first output bit and the third output bit based on the state of the first select signal. - View Dependent Claims (10)
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9. (canceled)
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11-20. -20 (canceled)
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21. A compressor, comprising:
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a first circuit having one or more of first and second partial product bits input on first and second input terminals of the first circuit, wherein the first circuit is configured to perform an XOR or XNOR logic operation on the first partial product bit or the second partial product bit to generate a resultant respective XOR or XNOR logic operation bit corresponding to one or more first select signals; and a second circuit having one or more of third and fourth partial product bits input on first and second input terminals of the second circuit, wherein the second circuit is configured to perform an XOR or XNOR logic operation on the third partial product bit or the fourth partial product bit to generate a resultant respective XOR or XNOR logic operation bit corresponding to one or more second select signals. - View Dependent Claims (22, 23, 24, 25)
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Specification