×

Data Compressor Logic Circuit

  • US 20200136643A1
  • Filed: 10/25/2018
  • Published: 04/30/2020
  • Est. Priority Date: 10/25/2018
  • Status: Active Grant
First Claim
Patent Images

1. A compressor, comprising:

  • first, second, and third logic gates each having respective first and second input terminals and an output terminal, wherein the first, second, and third logic gates are configured to output respective first, second, and third partial product bits at the respective output terminals;

    a first circuit having first and second input terminals electrically coupled to the respective output terminals of the first and second logic gates, wherein the first circuit is configured to perform an XOR or XNOR logic operation on the first partial product bit or the second partial product bit to generate a resultant respective XOR or XNOR logic operation bit corresponding to one or more select signals; and

    a first multiplexer having;

    a first multiplexer select input terminal electrically coupled to the first circuit, anda first multiplexer output terminal,wherein the first multiplexer is configured to select a carry-out bit from among at least the first partial product bit and a third partial product bit based on the one or more select signals received at the first multiplexer select input terminal.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×