DECODING METHOD FOR LOW-DENSITY PARITY-CHECK CODE AND SYSTEM THEREOF

• US 20200136646A1
• Filed: 05/13/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: CHANG, CHE-CHIA
• Granted Patent: US 10,826,528 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: H03M 13/1105 Decoding
• CPC Class Codes: H03M 13/1131 Scheduling of bit node or check node processing
• CPC Class Codes: H03M 13/616 Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
• CPC Class Codes: H03M 13/6519 Support of multiple transmission or communication standards
• CPC Class Codes: H03M 13/6566 Implementations concerning memory access contentions

Abstract

A decoding method for low-density parity-check (LDPC) code is provided and is configured to decode a communication protocol, which is pending to be tested. The communication protocol includes a code word, and the code word includes a code rate. The decoding method includes: receiving the code word of the communication protocol, which is pending to be tested; determining a parity-check matrix according to the code rate of the code word and saving the parity-check matrix in a dynamic memory; moving the parity-check matrix from the dynamic memory to a first memory and saving the code word in a second memory; sequentially transmitting the code word from the second memory to a plurality of check node units to calculate according to the parity-check matrix in the first memory; transmitting the code word verified by the check node units back to the second memory.

Claims

1. An decoding method for low-density parity-check code used to verify a communication protocol, which is pending to be tested, and the communication protocol having a code word and the code word having a code rate, the decoding method comprising:

receiving the code word of the communication protocol;

searching a parity-check matrix according to the code rate of the code word and saving the parity-check matrix in a dynamic memory;

moving the parity-check matrix from the dynamic memory to a first memory, and saving the code word in a second memory;

sequentially transmitting the code word from the second memory to a plurality of check node units according to the parity-check matrix saved in the first memory and verifying the code word in the check node units; and

transmitting the code word verified in the check node units back to the second memory.

2. The decoding method according to claim 1, wherein in the step of searching the parity-check matrix according to the code rate of the code word, the corresponding parity-check matrix is saved from an external storage medium to the dynamic memory according to the code rate via a look-up table.

3. The decoding method according to claim 1, wherein in the step of moving the parity-check matrix from the dynamic memory to the first memory, the parity-check matrix is moved from the dynamic memory to the first memory by a direct memory access controller.

4. The decoding method according to claim 1, wherein in the step of moving the parity-check matrix from the dynamic memory to the first memory and saving the code word in the second memory, the parity-check matrix is saved from the dynamic memory to the first memory and the code word in the second memory is saved at the same time.

5. The decoding method according to claim 1, wherein in the step of sequentially transmitting the code word from the second memory to a plurality of the check node units according to the parity-check matrix saved in the first memory and verifying the code word in the check node units, the code word from the second memory is sequentially transmitted to the check node units through a first shifter to be verified.

6. The decoding method according to claim 5, wherein in the step of transmitting the code word verified in the check node units back to the second memory, the code word verified by the check node units will be transmitted and saved in a buffer and the verified code word is transmitted from the buffer to the second memory through the check node units and a second shifter.

7. An decoding method for low-density parity-check code used to verify a communication protocol, which is pending to be tested, and the communication protocol having a code word and the code word having a code rate, the decoding method comprising:

saving a plurality of parity-check matrixes in a dynamic memory;

receiving the code word of the communication protocol;

searching one of the parity-check matrixes according to the code rate of the code word;

moving one of the parity-check matrixes from the dynamic memory to a first memory, and saving the code word in a second memory;

sequentially transmitting the code word from the second memory to a plurality of check node units according to one of the parity-check matrixes saved in the first memory and verifying the code word in the check node units; and

transmitting the code word verified in the check node units back to the second memory.

8. The decoding method according to claim 7, wherein in the step of searching the parity-check matrix according to the code rate of the code word, the corresponding parity-check matrix in the dynamic memory is saved from an external storage medium according to the code rate via a look-up table manner.

9. The decoding method according to claim 7, wherein in the step of moving the parity-check matrix from the dynamic memory to the first memory, a direct memory access controller is implemented to move the parity-check matrix from the dynamic memory to the first memory.

10. The decoding method according to claim 7, wherein in the step of moving the parity-check matrix from the dynamic memory to the first memory and saving the code word in the second memory, the parity-check matrix is saved from the dynamic memory to the first memory and save the code word in the second memory at the same time.

11. The decoding method according to claim 7, wherein in the step of sequentially transmitting the code word from the second memory to a plurality of the check node units according to the parity-check matrix saved in the first memory and verifying the code word in the check node units, the code word is sequentially transmitted from the second memory to the check node units through a first shifter and verifying the code word in the check node units.

12. The decoding method according to claim 11, wherein in the step of transmitting the code word verified in the check node units back to the second memory, the code word is verified by the check node units will be transmitted and saved in a buffer and the verified code word is transmitted from the buffer to the second memory through the check node units and a second shifter.

13. A decoding system for low-density parity-check code used to verify a communication protocol, which is pending to be tested, and the communication protocol having a code word and the code word having a code rate, and the decoding system comprising:

a dynamic memory configured to save at least one parity-check matrix;

a first memory electrically connected to the dynamic memory and configured to save the at least one parity-check matrix transmitted from the dynamic memory;

a second memory electrically connected to the first memory and configured to save data of the code word;

a plurality of check node units connected to the second memory and configured to receive and calculate the code word respectively; and

a buffer electrically connected to the check node units and configured to save the code word verified by the check note units.

14. The decoding system of claim 13, further comprising:

a first shifter electrically connected to the second memory and the check note units, and configured to sequentially read and transmit the code word to each of the check note units; and

a second shifter electrically connected to the second memory and the check note units, and configured to sequentially transmit the verified code word back to the second memory.

15. The decoding system of claim 13, further comprising a direct memory access controller configured to move the at least one parity-check matrix from the dynamic memory to the first memory.

16. The decoding system of claim 13, wherein in the decoding system, the at least one parity-check matrix is saved in the dynamic memory according to the code rate of the code word.

17. The decoding system of claim 13, wherein in the decoding system, the at least one parity-check matrix is saved from a storage medium to the dynamic memory.

18. The decoding system of claim 13, wherein the communication protocols are digital video broadcasting communication protocols.

19. The decoding system of claim 13, wherein the dynamic memory is dynamic random access memory (DRAM).

20. The decoding system of claim 13, wherein the first memory and the second memory are static random access memories (SRAM).