SYSTEM AND METHOD FOR TRANSFERRING DATA AND A DATA CHECK FIELD

• US 20200136754A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hoermaier, Klaus, Barrenscheen, Jens, Heiling, Christian, Hofer, Guenter
• Granted Patent: US 10,841,039 B2
• Time in Patent Office: Days
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 2001/0094 Bus

Abstract

In accordance with an embodiment, a method of transferring data includes determining, by a first device, a data check field of a data frame based on a predetermined identification field and a plurality of data bits, wherein the predetermined identification field represents at least one of a content, source or target of the plurality of data bits; and transmitting, by the first device to a second device, the data frame comprising the plurality of data bits and the data check field without directly transmitting the predetermined identification field.

Claims

1. A method of transferring data, the method comprising:

determining, by a first device, a data check field of a data frame based on a predetermined identification field and a plurality of data bits, wherein the predetermined identification field represents at least one of a content, source or target of the plurality of data bits; and

transmitting, by the first device to a second device, the data frame comprising the plurality of data bits and the data check field without directly transmitting the predetermined identification field.

2. The method of claim 1, wherein the source of the plurality of data bits is based on a decoded read address.

3. The method of claim 1, wherein the target of the plurality of data bits is based on a decoded write address.

4. The method of claim 1, wherein the source of the plurality of data bits is based on a device identifier of the first device or an address of the first device.

5. The method of claim 1, wherein determining the data check field comprises applying a hash function to the predetermined identification field and the plurality of data bits to produce the data check field.

6. The method of claim 1, wherein determining the data check field comprises:

performing a reversible operation with the plurality of data bits and the predetermined identification field to produce a first data value; and

applying a hash function to the first data value to produce the data check field.

7. The method of claim 6, wherein:

the reversible operation comprises an exclusive-OR operation; and

applying the hash function comprises calculating a cyclic redundancy checksum from the plurality of data bits.

8. The method of claim 1, wherein determining the data check field comprises:

applying a hash function to the plurality of data bits to produce a first checksum; and

performing a reversible operation with the first checksum and the predetermined identification field to produce the data check field.

9. The method of claim 1, wherein the predetermined identification field comprises a write address to which first received data is written.

10. The method of claim 9, further comprising receiving, by the second device, the first received data and the write address from the first device before determining the data check field.

11. The method of claim 10, wherein the first received data comprises a plurality of data words and the write address comprises a plurality of write addresses.

12. The method of claim 1, further comprising:

receiving, by the second device, the plurality of data bits and the data check field from the first device; and

determining, by the second device, the predetermined identification field by verifying the data check field based on the received plurality of data bits and a locally stored version of the predetermined identification field.

13. A circuit configured to be coupled to a bus, the circuit comprising:

a first circuit configured to determine a data check field of a data frame based on a predetermined identification field and a plurality of data bits, wherein the predetermined identification field represents at least one of a content, source or target of the plurality of data bits; and

a transmitter coupled to the first circuit and configured to be coupled to the bus and to transmit to a second circuit the data frame comprising the plurality of data bits and the data check field without directly transmitting the predetermined identification field.

14. The circuit of claim 13, wherein the first circuit and the transmitter are disposed on a battery cell integrated circuit configured to be coupled to a battery cell, and wherein the second circuit is a host controller.

15. The circuit of claim 13, wherein the first circuit is configured to determine the data check field by:

performing a reversible operation with the plurality of data bits and the predetermined identification field to produce a first data value; and

applying a hash function to the first data value to produce the data check field.

16. The circuit of claim 13, wherein the first circuit is configured to determine the data check field by:

applying a hash function to the plurality of data bits to produce a first checksum; and

performing a reversible operation with the first checksum and the predetermined identification field to produce the data check field.

17. The circuit of claim 13, wherein the second circuit is configured to be coupled to the bus and comprises a receiver configured to receive the plurality of data bits and the data check field from the transmitter, wherein the second circuit is configured to determine the predetermined identification field by verifying the data check field based on the received plurality of data bits and a locally stored version of the predetermined identification field.

18. The circuit of claim 17, wherein the transmitter, receiver, first circuit and second circuit are disposed on a monolithic semiconductor circuit.

19. An integrated circuit comprising:

a bus;

a bus master circuit coupled to the bus; and

a data storage circuit coupled to the bus, the data storage circuit comprising a data storage area, an address decoder, and a read checksum generator, the data storage circuit configured to

receive a read address from the bus,

decode, by the address decoder, the received read address to produce a decoded read address,

access data from the data storage area based on the decoded read address,

produce, by the read checksum generator, a read data check field based on the accessed data and the decoded read address, and

transmit the read data check field on the bus without directly transmitting the decoded read address.

20. The integrated circuit of claim 19, wherein the data storage circuit further comprises a write checksum circuit, and the data storage circuit is further configured to:

receive a write address, write data, and a first write data check field from the bus,

decode, using the address decoder, the received write address to produce a decoded write address,

select the data storage area based on the decoded write address,

read verification data from the selected data storage area based on the decoded write address after writing the write data,

produce, using the write checksum circuit, a second write data check field based on the decoded write address and the verification data,

compare, using the write checksum circuit, the first write data check field to the second write data check field, and

write the write data to the selected data storage area if the first write data check field matches the second write data check field.

21. The integrated circuit of claim 19, wherein the data storage circuit is further configured to transmit the accessed data on the bus.