I/O CIRCUIT DESIGN FOR SRAM-BASED PUF GENERATORS

• US 20200136839A1
• Filed: 04/12/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TSAI, Jui-Che, LU, Shih-Lien Linus, LEE, Cheng Hung, HUANG, Chia-En
• Granted Patent: US 10,972,292 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H04L 2209/122 Hardware reduction or efficient architectures
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
• CPC Class Codes: H04L 9/3278 using physically unclonable functions [PUF]

Abstract

Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Claims

1. A physical unclonable function (PUF) generator comprising:

a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and

at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array,

wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and

based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

2. The PUF generator of claim 1, wherein the SA is coupled between two first bit lines from the at least two neighboring columns of the PUF cell array.

3. The PUF generator of claim 2, wherein the two first bit lines coupled to the SA are separated by a first distance, wherein the first distance is smaller than a second distance, wherein the second distance is a distance separated between two second bit lines from the at least two neighboring columns.

4. The PUF generator of claim 2, wherein the two cross-coupled inverters in the SA each is coupled directly to the two first bit lines of the at least two neighboring columns with no access transistor.

5. The PUF generator of claim 1, wherein the two cross-coupled inverters in the SA each comprise an n-type metal-oxide-semiconductor (NMOS) transistor and a p-type MOS (PMOS) transistor.

6. The PUF generator of claim 1, further comprising:

at least two pass gates, wherein the at least two pass gates each is coupled between the SA and the PUF cell array, wherein the at least two pass gates each comprises a transmission gate, wherein the transmission gate comprise at least 2 transistors.

7. The PUF generator of claim 1, further comprising:

at least one pre-discharge transistor, wherein the at least one pre-discharge transistor is coupled between a first voltage and at least one respective bit line of the at least two neighboring columns.

8. The PUF generator of claim 1, further comprising:

at least one equalizer, wherein each of the at least one equalizers is coupled between two respective bit lines of the at least two neighboring columns.

9. The PUF generator of claim 1, wherein the plurality of bit cells each comprises a single transistor.

10. A method for generating a physical unclonable function (PUF) signature comprising:

writing a first voltage in each of a plurality of bit cells in at least two neighboring columns of a PUF cell array through an input/output (I/O) circuit;

stabilizing the first voltage level to a second voltage level in each of the plurality of bit cells;

enabling a sense amplifier (SA) of the I/O circuit to read two second voltage levels from the at least two neighboring columns; and

determining a PUF signature,

wherein the I/O circuit comprises no cross-coupled pair of transistors, and wherein the SA comprises two first cross-coupled inverters with no access transistor and a SA enable transistor.

11. The method of claim 10, wherein the writing is performed by turning on at least one pre-charge transistors, wherein the at least one pre-discharge transistor is coupled between a first voltage and at least one respective bit line of the at least two neighboring columns.

12. The method of claim 10, wherein the writing further comprising:

turning on at least two access transistors in each of the plurality of bit cells, when each of the plurality of bit cells in the PUF cell array comprises two second cross-coupled inverters.

13. The method of claim 10, wherein the stabilizing comprising:

turning off at least two access transistors in each of the plurality of bit cells, when each of the plurality of bit cells in the PUF cell array comprises two second cross-coupled inverters.

14. The method of claim 10, wherein the SA is coupled between two first bit lines from the two neighboring columns of the PUF cell array.

15. The method of claim 14, wherein the two first bit lines coupled to the SA are separated by a first distance, wherein the first distance is smaller than a second distance, wherein the second distance is a distance separated between two second bit lines from the at least two neighboring columns.

16. The method of claim 10, wherein each of the two first cross-coupled inverters in the SA is coupled directly to the two first bit lines of the at least two neighboring columns with no access transistor.

17. The method of claim 10, wherein the I/O circuit further comprising one of the following:

at least two pass gates, at least one pre-discharge transistor, and at least one equalizer, wherein each of the at least two pass gates comprises a transmission gate, wherein the transmission gate comprise at least 2 transistors, wherein each of the at least one pre-discharge transistor is coupled between a first voltage and at least one respective bit line of the at least two neighboring columns, wherein each of the at least one equalizers is coupled between two respective bit lines of the at least two neighboring columns.

18. A physical unclonable function (PUF) generator comprising:

a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein the plurality of bit cells each comprises two first cross-coupled inverters and two access transistors, wherein the two access transistors are coupled to a first bit line and a second bit line of in a respective column, and

a plurality of input/output (I/O) circuit each coupled to two neighboring columns of the PUF cell array,

wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two second cross-coupled inverters with no access transistor and a SA enable transistor, and wherein each of the two second cross-coupled inverters in the SA comprises an n-type metal-oxide-semiconductor (NMOS) transistor and a p-type MOS (PMOS) transistor.

19. The PUF generator of claim 18, wherein each of the two second cross-coupled inverters in the SA is coupled directly to the two first bit lines of the two neighboring columns with no access transistor, wherein the two first bit lines coupled to the SA are separated by a first distance, wherein the first distance is smaller than a second distance, wherein the second distance is a distance separated between two second bit lines from the two neighboring columns.

20. The PUF generator of claim 18, wherein the I/O circuit further comprising:

at least two pass gates, at least one pre-discharge transistor, and at least one equalizer, wherein each of the at least two pass gates comprises a transmission gate, wherein the transmission gate comprise at least 2 transistors, wherein each of the at least one pre-discharge transistor is coupled between a first voltage and at least one respective bit line of the at least two neighboring columns, wherein each of the at least one equalizers is coupled between two respective bit lines of the at least two neighboring columns.