PUF CELL ARRAY, SYSTEM AND METHOD OF MANUFACTURING SAME

• US 20200136840A1
• Filed: 10/23/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LEE, Cheng-En, LU, Shih-Lien Linus
• Granted Patent: US 11,461,525 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics

Abstract

A physically unclonable function (PUF) cell array includes a first PUF cell arranged in a first column in a first direction and a second PUF cell arranged in a second column in the first direction. The first PUF cell includes a first set of conductive structures extending in the first and a second direction. The second PUF cell includes a second set of conductive structures extending in the first and the second direction. The first PUF cell includes a first conductive structure and a second conductive structure extending in the second direction. The second PUF cell includes a third conductive structure and a fourth conductive structure extending in the second direction. The first and third conductive structure or the second and fourth conductive structure are symmetric to each other with respect to a central line of at least the first or second PUF cell extending in the second direction.

Claims

1. A physically unclonable function (PUF) cell array comprising:

a first PUF cell arranged in a first column in a first direction, the first PUF cell comprising;

a first set of conductive structures extending in the first direction and a second direction different from the first direction, the first set of conductive structures being on a first metal layer, and including a first conductive structure extending in at least the second direction and a second conductive structure extending in at least the second direction and being separated from the first conductive structure in the first direction; and

a second PUF cell arranged in a second column in the first direction, the second PUF cell comprising;

a second set of conductive structures extending in the first direction and the second direction, being on the first metal layer and including a third conductive structure extending in at least the second direction and a fourth conductive structure extending in at least the second direction and being separated from the third conductive structure in the first direction;

wherein at least the first conductive structure and the third conductive structure, or the second conductive structure and the fourth conductive structure are symmetric to each other with respect to a central line of at least the first PUF cell or the second PUF cell extending in the second direction.

2. The PUF cell array of claim 1, further comprising:

a first set of PUF cells having a first number of PUF cells, the first set of PUF cells including the first PUF cell; and

a second set of PUF cells having a second number of PUF cells equal to the first number of PUF cells, the second set of PUF cells including the second PUF cell.

3. The PUF cell array of claim 2, wherein

each PUF cell of the first set of PUF cells and the second set of PUF cells has a corresponding output pin having a corresponding address, and

each address of each corresponding output pin of each PUF cell in the first set of PUF cells and the second set of PUF cells is randomly arranged.

4. The PUF cell array of claim 1, further comprising:

a third PUF cell arranged in a first row in the second direction, the third PUF cell and the first PUF cell are symmetric to each other with respect to a first line in the first direction, the third PUF cell comprising;

a third set of conductive structures extending in at least the second direction, being on the first metal layer, and including a fifth conductive structure extending in at least the second direction and a sixth conductive structure extending in at least the second direction and being separated from the fifth conductive structure in the first direction; and

a fourth PUF cell arranged in the first row, the fourth PUF cell and the second PUF cell are symmetric to each other with respect to a second line in the first direction, the fourth PUF cell comprising;

a fourth set of conductive structures extending in at least the second direction, and being on the first metal layer, and including a seventh conductive structure extending in at least the second direction and an eighth conductive structure extending in at least the second direction and being separated from the seventh conductive structure in the first direction;

wherein at least the fifth conductive structure and the seventh conductive structure, or the sixth conductive structure and the eighth conductive structure are symmetric to each other with respect to a central line of at least the third PUF cell or the fourth PUF cell extending in the second direction; and

the first PUF cell and the second PUF cell are arranged in a second row in the second direction.

5. The PUF cell array of claim 4, wherein

the third PUF cell is arranged in the first column;

the fourth PUF cell is arranged in the second column;

the first row is adjacent to the second row; and

the first column is adjacent to the second column.

6. The PUF cell array of claim 4, wherein

the fourth PUF cell is arranged in the first column;

the third PUF cell is arranged in the second column;

the first row is adjacent to the second row; and

the first column is adjacent to the second column.

7. The PUF cell array of claim 1, wherein

the first PUF cell further comprises:

a first inverter; and

a second inverter cross-coupled to the first inverter;

the second PUF cell further comprises;

a third inverter; and

a fourth inverter cross-coupled to the third inverter.

8. The PUF cell array of claim 7, wherein

the first conductive structure and the fourth conductive structure are separated from each other in the second direction;

the second conductive structure and the third conductive structure are separated from each other in the second direction;

the first conductive structure and the second conductive structure cross-couple the first inverter to the second inverter; and

the fourth conductive structure and the third conductive structure cross-couple the third inverter to the fourth inverter.

9. The PUF cell array of claim 8, wherein

the first inverter comprises:

a first n-type transistor; and

a first p-type transistor;

the second inverter comprises;

a second n-type transistor; and

a second p-type transistor;

the third inverter comprises;

a third n-type transistor; and

a third p-type transistor;

the fourth inverter comprises;

a fourth n-type transistor; and

a fourth p-type transistor;

the first PUF cell further comprises;

a fifth n-type transistor; and

a sixth n-type transistor; and

the second PUF cell further comprises;

a seventh n-type transistor; and

an eighth n-type transistor.

10. The PUF cell array of claim 9, wherein

a gate of the first n-type transistor and a gate of the first p-type transistor are cross-coupled to at least a drain of the second n-type transistor, a drain of the second p-type transistor and a drain of the fifth n-type transistor by at least the first conductive structure;

a gate of the second n-type transistor and a gate of the second p-type transistor are cross-coupled to at least a drain of the first n-type transistor, a drain of the first p-type transistor and a drain of the sixth n-type transistor by at least the second conductive structure;

a gate of the third n-type transistor and a gate of the third p-type transistor are cross-coupled to at least a drain of the fourth n-type transistor, a drain of the fourth p-type transistor and a drain of the seventh n-type transistor by at least the third conductive structure; and

a gate of the fourth n-type transistor and a gate of the fourth p-type transistor are cross-coupled to at least a drain of the third n-type transistor, a drain of the third p-type transistor and a drain of the eighth n-type transistor by at least the second conductive structure.

11. The PUF cell array of claim 1, wherein

the first PUF cell further comprises:

a first conductive portion extending in the first direction;

a second conductive portion extending in the first direction, and overlapping the first set of conductive structures; and

a third conductive portion extending in the first direction;

each of the first conductive portion, the second conductive portion and the third conductive portion being separated from each other in the second direction, and being on a second metal layer different from the first metal layer;

the second PUF cell further comprises;

a fourth conductive portion extending in the first direction;

a fifth conductive portion extending in the first direction, and overlapping the second set of conductive structures; and

a sixth conductive portion extending in the first direction;

each of the fourth conductive portion, the fifth conductive portion and the sixth conductive portion being separated from each other in the second direction, and being on the second metal layer.

12. A method of forming a physically unclonable function (PUF) cell array, the method comprising:

generating a first layout design of a first PUF cell, the first layout design being arranged in a first column in a first direction, the generating the first layout design comprising;

generating a first set of conductive feature layout patterns extending in the first direction and a second direction different from the first direction, the first set of conductive feature layout patterns being on a first layout level, and including a first conductive feature layout pattern extending in at least the second direction and a second conductive feature layout pattern extending in at least the second direction and being separated from the first conductive feature layout pattern in the first direction;

generating a second layout design of a second PUF cell, the second layout design being arranged in a second column in the first direction, the generating the second layout design comprising;

generating a second set of conductive feature layout patterns extending in the first direction and the second direction, the second set of conductive feature layout patterns being on the first layout level, and including a third conductive feature layout pattern extending in at least the second direction and a fourth conductive feature layout pattern extending in at least the second direction and being separated from the third conductive feature layout pattern in the first direction; and

wherein at least the first conductive feature layout pattern and the third conductive feature layout pattern, or the second conductive feature layout pattern and the fourth conductive feature layout pattern are symmetric to each other with respect to a central line of at least the first layout design or the second layout design extending in the second direction, at least one of the above generating operations is performed by a hardware processor, and at least the first layout design or the second layout design is stored in a non-transitory computer-readable medium; and

manufacturing the PUF cell array based on at least the first layout design or the second layout design.

13. The method of claim 12, further comprising:

generating a third layout design of a third PUF cell, the third layout design being arranged in a first row in the second direction, the third layout design and the first layout design are symmetric to each other with respect to a first line in the first direction, the generating the third layout design comprising;

generating a third set of conductive feature layout patterns extending in the first direction and the second direction, the third set of conductive feature layout patterns being on the first layout level, and including a fifth conductive feature layout pattern extending in at least the second direction and a sixth conductive feature layout pattern extending in at least the second direction and being separated from the fifth conductive feature layout pattern in the first direction;

generating a fourth layout design of a fourth PUF cell, the fourth layout design being arranged in the first row, the fourth layout design and the second layout design are symmetric to each other with respect to a second line in the first direction, the generating the fourth layout design comprising;

generating a fourth set of conductive feature layout patterns extending in the first direction and the second direction, the fourth set of conductive feature layout patterns being on the first layout level and including a seventh conductive feature layout pattern extending in at least the second direction and an eighth conductive feature layout pattern extending in at least the second direction and being separated from the seventh conductive feature layout pattern in the first direction;

wherein at least the fifth conductive feature layout pattern and the seventh conductive feature layout pattern, or the sixth conductive feature layout pattern and the eighth conductive feature layout pattern are symmetric to each other with respect to a central line of at least the third layout design or the fourth layout design extending in the second direction; and

the first layout design and the second layout design are arranged in a second row in the second direction.

14. The method of claim 13, wherein

the third layout design is arranged in the first column;

the fourth layout design is arranged in the second column;

the first row is adjacent to the second row; and

the first column is adjacent to the second column.

15. The method of claim 13, wherein

the fourth layout design is arranged in the first column;

the third layout design is arranged in the second column;

the first row is adjacent to the second row; and

the first column is adjacent to the second column.

16. The method of claim 12, further comprising:

generating a first set of layout designs of a first set of PUF cells, the first set of layout designs including the first layout design, the first set of PUF cells including the first PUF cell, the first set of layout designs having a first number of first layout designs; and

generating a second set of layout designs of a second set of PUF cells, the second set of layout designs including the second layout design, the second set of PUF cells including the second PUF cell, the second set of layout designs having a second number of second layout designs equal to the first number of first layout designs.

17. The method of claim 12, wherein

the generating the first layout design further comprises:

generating a third set of conductive feature layout patterns extending in the first direction, overlapping at least the first set of conductive feature layout patterns, being located on a second layout level different from the first layout level, and each conductive feature layout pattern of the third set of conductive feature layout patterns being separated from an adjacent layout pattern of the third set of conductive feature layout patterns in at least the second direction; and

the generating the second layout design further comprises;

generating a fourth set of conductive feature layout patterns extending in the first direction, overlapping at least the second set of conductive feature layout patterns, being located on the second layout level, and each conductive feature layout pattern of the fourth set of conductive feature layout patterns being separated from an adjacent layout pattern of the fourth set of conductive feature layout patterns in at least the second direction.

18. A system for designing a physically unclonable function (PUF) cell array, the system comprises:

a non-transitory computer readable medium configured to store executable instructions; and

a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for;

placing a first layout design of a first PUF cell in a first column in a first direction, the placing the first layout design comprising;

placing a first set of conductive feature layout patterns on a first layout level, the first set of conductive feature layout patterns extending in the first direction and a second direction different from the first direction, and including a first conductive feature layout pattern extending in at least the second direction and a second conductive feature layout pattern extending in at least the second direction and being separated from the first conductive feature layout pattern in the first direction;

placing a second layout design of a second PUF cell in a second column in the first direction, the placing the second layout design comprising;

placing a second set of conductive feature layout patterns on the first layout level, the second set of conductive feature layout patterns extending in the first direction and the second direction, and including a third conductive feature layout pattern extending in at least the second direction and a fourth conductive feature layout pattern extending in at least the second direction and being separated from the third conductive feature layout pattern in the first direction;

wherein at least the first conductive feature layout pattern and the third conductive feature layout pattern, or the second conductive feature layout pattern and the fourth conductive feature layout pattern are symmetric to each other with respect to a first central line of at least the first layout design or the second layout design extending in the second direction.

19. The system of claim 18, wherein the processor configured to execute instructions for placing the first set of conductive feature layout patterns further comprises:

placing a fifth conductive feature layout pattern and a sixth conductive feature layout pattern on the first layout level, extending in at least the second direction and being separated from each other in the second direction, the fifth conductive feature layout pattern being separated from the second conductive feature layout pattern in the first direction by a first distance, the sixth conductive feature layout pattern being separated from the first conductive feature layout pattern in the first direction by a second distance different from the first distance; and

placing a first set of gate layout patterns on a second layout level different from the first layout level, the first set of gate layout patterns extending in the first direction, and being overlapped by the first conductive feature layout pattern and the second conductive feature layout pattern.

20. The system of claim 19, wherein the processor configured to execute instructions for placing the second set of conductive feature layout patterns further comprises:

placing a seventh conductive feature layout pattern and an eighth conductive feature layout pattern on the first layout level, extending in at least the second direction and being separated from each other in the second direction, the seventh conductive feature layout pattern being separated from the fourth conductive feature layout pattern in the first direction by the second distance, the eighth conductive feature layout pattern being separated from the third conductive feature layout pattern in the first direction by the first distance; and

placing a second set of gate layout patterns on the second layout level, the second set of gate layout patterns extending in the first direction, and being overlapped by the fourth conductive feature layout pattern and the third conductive feature layout pattern;

wherein at least the fifth conductive feature layout pattern and the sixth conductive feature layout pattern, or the seventh conductive feature layout pattern and the eighth conductive feature layout pattern are symmetric to each other with respect to a second central line of at least the first layout design or the second layout design extending in the first direction.