CIRCUITS AND METHODS FOR BI-DIRECTIONAL DATA COMMUNCTION OVER ISOLATION CHANNELS

• US 20200136869A1
• Filed: 12/30/2019
• Published: 04/30/2020
• Est. Priority Date: 08/23/2017
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: REHMAN, Syed Enam, CONSTANTINO, John
• Granted Patent: US 10,972,323 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04B 3/34 by systematic interconnection of lengths of cable during laying; by addition of balancing components to cable during laying
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/2071 in which the data are represented by the carrier phase, e.g. systems with differential coding

Abstract

In a general aspect, a data communication circuit can include a differential transmitter configured to be coupled with a differential input of a first unidirectional differential isolation channel, and a differential receiver configured to be coupled with a differential output of a second unidirectional differential isolation channel. The differential receiver can include a comparator that has a threshold that is adjustable based on a signal received via the second unidirectional differential isolation channel.

Claims

1. A data communication circuit comprising:

a differential transmitter configured to be coupled with a differential input of a first unidirectional differential isolation channel; and

a differential receiver configured to be coupled with a differential output of a second unidirectional differential isolation channel,

the differential receiver including a comparator having a threshold adjustable based on a signal received via the second unidirectional differential isolation channel.

2. The data communication circuit of claim 1, wherein:

the data communication circuit is a first data communication circuit; and

the signal received via the second unidirectional differential isolation channel is a clock signal of a second data communication circuit coupled with the second unidirectional differential isolation channel.

3. The data communication circuit of claim 1, wherein the differential receiver includes:

a full-wave rectifier configured to detect an envelope of a differential On/Off keyed radio-frequency signal received via the second unidirectional differential isolation channel, the full-wave rectifier and the comparator are configured to convert the differential On/Off keyed radio-frequency signal to a baseband digital bit stream.

4. The data communication circuit of claim 3, wherein the baseband digital bit stream is an encoded digital bit stream, the data communication circuit further comprising:

a decoder coupled with the differential receiver, the decoder being configured to;

recover a clock signal from the encoded digital bit stream, the recovered clock signal corresponding with the signal received via the second unidirectional differential isolation channel, the recovered clock signal being recovered using a delay that is proportional to a period of the signal received via the second unidirectional differential isolation channel; and

decode the encoded digital bit stream using the recovered clock signal to produce a decoded digital bit stream.

5. The data communication circuit of claim 4, wherein the decoded digital bit stream is a serialized digital bit stream, the data communication circuit further comprising:

a deserializer configured to, using the recovered clock signal, deserialize the serialized digital bit stream to a plurality of output bits.

6. The data communication circuit of claim 4, wherein the delay is determined from a 50 percent duty cycle square wave envelope detection signal produced by the full-wave rectifier.

7. The data communication circuit of claim 1, further comprising a crosstalk suppression circuit configured to suppress crosstalk between the differential transmitter and the differential receiver due to parasitic capacitive coupling between the first unidirectional differential isolation channel and the second unidirectional differential isolation channel.

8. The data communication circuit of claim 7, wherein the crosstalk suppression circuit is configured to provide:

via a first adjustable capacitance circuit, a first negative feedback signal applied between a positive output terminal of the differential transmitter and a negative input terminal of the differential receiver; and

via a second adjustable capacitance circuit, a second negative feedback signal applied between a negative output terminal of the differential transmitter and a positive input terminal of the differential receiver,

the first negative feedback signal and the second negative feedback signal being configured to suppress crosstalk between the differential transmitter and the differential receiver due to parasitic capacitive coupling between the first unidirectional differential isolation channel and the second unidirectional differential isolation channel in a common dielectric substrate.

9. The data communication circuit of claim 8, wherein the data communication circuit is configured to adjust respective capacitances of the first adjustable capacitance circuit and the second adjustable capacitance circuit based on a calibration signal, the calibration signal providing an indication of the parasitic capacitive coupling between the first unidirectional differential isolation channel and the second unidirectional differential isolation channel.

10. The data communication circuit of claim 1, wherein the differential receiver includes an LC resonant circuit having a corner frequency, the LC resonant circuit being configured to attenuate signals with frequencies below the corner frequency.

11. A data communication device comprising:

a dielectric substrate including;

a first capacitor and a second capacitor defined thereon, the first capacitor and the second capacitor being included in a first unidirectional differential isolation channel having a differential input and a differential output, and

a third capacitor and a fourth capacitor defined thereon, the third capacitor and the fourth capacitor being included in a second unidirectional differential channel having a differential input and a differential output,

a first data communication circuit including;

a differential transmitter coupled with the differential input of the first unidirectional differential isolation channel, and

a differential receiver coupled with the differential output of the second unidirectional differential channel,

a second data communication circuit including;

a differential transmitter coupled with the differential input of the second unidirectional differential channel, and

a differential receiver coupled with the differential output of the second unidirectional differential channel,

the differential receiver of the first data communication circuit including a comparator having a threshold adjustable based on a clock signal provided by a transmitter of the second data communication circuit via the second unidirectional differential channel,

the differential receiver of the second data communication circuit including a comparator having a threshold adjustable based on a clock signal provided by the transmitter of the first data communication circuit via the first unidirectional differential isolation channel.

12. The data communication device of claim 11, wherein the differential receiver of the first data communication circuit includes:

a full-wave rectifier configured to detect an envelope of a differential On/Off keyed radio-frequency signal received from the transmitter of the second data communication circuit, the full-wave rectifier and the comparator of the first data communication circuit are configured to convert the differential On/Off keyed radio-frequency signal to a baseband digital bit stream.

13. The data communication device of claim 12, wherein the baseband digital bit stream is an encoded digital bit stream, the first data communication circuit further comprising:

a decoder coupled with the differential receiver of the first data communication circuit, the decoder being configured to;

recover a clock signal from the encoded digital bit stream, the recovered clock signal corresponding with the clock signal of the second data communication circuit, the recovered clock signal being recovered using a delay that is proportional to a period of the clock signal of the second data communication circuit; and

decode the encoded digital bit stream using the recovered clock signal to produce a decoded digital bit stream.

14. The data communication device of claim 11, the first data communication circuit further including a crosstalk suppression circuit configured to suppress crosstalk between the differential transmitter and the differential receiver of the first data communication circuit due to parasitic capacitive coupling between the first unidirectional differential isolation channel and the second unidirectional differential channel in the dielectric substrate.

15. A method comprising:

providing, via a first unidirectional isolation channel, a first calibration signal from a transmitter of a first data communication circuit to a receiver of a second data communication circuit, the first calibration signal being based on a clock signal of the first data communication circuit;

providing, via a second unidirectional isolation channel, a second calibration signal from a transmitter of the second data communication circuit to a receiver of the first data communication circuit, the second calibration signal being based on a clock signal of the first data communication circuit;

determining, by the first data communication circuit, based on the second calibration signal;

a threshold of a comparator included in the receiver of the first data communication circuit, and

a clock recovery delay for a decoder of the first data communication circuit; and

determining, by the second data communication circuit, based on the first calibration signal;

a threshold of a comparator included in the receiver of the second data communication circuit, and

a clock recovery delay for a decoder of the second data communication circuit.

16. The method of claim 15, further comprising, prior to providing the first calibration signal and providing the second calibration signal:

adjusting, by the first data communication circuit, a capacitance of a first crosstalk suppression circuit included in the first data communication circuit, the first crosstalk suppression circuit being configured to suppress crosstalk between a transmitter and a receiver of the first data communication circuit;

in response to determining that adjustment of the capacitance of the first crosstalk suppression circuit has been completed, adjusting, by the second data communication circuit, a capacitance of a second crosstalk suppression circuit included in the second data communication circuit, the second crosstalk suppression circuit being configured to suppress crosstalk between a transmitter and a receiver of the second data communication circuit.

17. The method of claim 16, wherein:

adjustment of the capacitance of the first crosstalk suppression circuit and adjustment of the capacitance of the second crosstalk suppression circuit are performed in response to a first handshake request and response between the first data communication circuit and the second data communication circuit;

providing the first calibration signal and providing the second calibration signal are performed in response to a second handshake request and response between the first data communication circuit and the second data communication circuit.

18. The method of claim 17, wherein occurrence of a fault condition in the first data communication circuit or the second data communication circuit causes the first data communication circuit and the second data communication circuit to repeat at least one of the first handshake request and response or the second handshake request and response.

19. The method of claim 15, further comprising after a startup process of the first data communication circuit, asserting a fault condition if the receiver of the first data communication circuit does not detect an incoming signal.