DATA PROCESSING DEVICE AND METHOD

• US 20200136872A1
• Filed: 12/31/2019
• Published: 04/30/2020
• Est. Priority Date: 07/31/2017
• Status: Active Grant

• Current Assignee: SZ DJI Technology Co., Ltd. (d/b/a DJI) (iFlight Technology Company Limited)
• Original Assignee: SZ DJI Technology Co., Ltd. (d/b/a DJI) (iFlight Technology Company Limited)
• Inventors: ZHAI, Chunhua, ZHU, Jianhua
• Granted Patent: US 10,887,145 B2
• Time in Patent Office: Days
• CPC Class Codes: H04B 7/04 using two or more spaced independent antennas
• CPC Class Codes: H04L 27/2605 Symbol extensions, e.g. Zero Tail, Unique Word [UW]
• CPC Class Codes: H04L 27/265 Fourier transform demodulators, e.g. fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators H04L27/26524 takes precedence
• CPC Class Codes: H04L 27/2665 Fine synchronisation, e.g. by positioning the FFT window
• CPC Class Codes: H04L 27/2697 in combination with other modulation techniques

Abstract

A data processing device includes a first circuit and a second circuit. The first circuit includes a first front-end circuit configured to process first data to obtain first demodulated data, and a back-end circuit coupled to the first front-end circuit and configured to receive the first demodulated data. The second circuit includes a second front-end circuit configured to process second data to obtain second demodulated data, and a transmitter coupled to the second front-end circuit and configured to transmit the second demodulated data to the first circuit. The back-end circuit is further configured to receive the second demodulated data, and process the first demodulated data and the second demodulated data.

Claims

1. A data processing device comprising:

a first circuit including;

a first front-end circuit configured to process first data to obtain first demodulated data; and

a back-end circuit coupled to the first front-end circuit and configured to receive the first demodulated data; and

a second circuit including;

a second front-end circuit configured to process second data to obtain second demodulated data; and

a transmitter coupled to the second front-end circuit and configured to transmit the second demodulated data to the first circuit,

wherein the back-end circuit is further configured to;

receive the second demodulated data, and

process the first demodulated data and the second demodulated data.

2. The data processing device of claim 1, wherein the first circuit further includes a storage medium coupled to the back-end circuit and configured to store the second demodulated data.

3. The data processing device of claim 2, wherein:

the transmitter is further configured to transmit the second demodulated data to the storage medium, and

the back-end circuit is further configured to read the second demodulated data from the storage medium.

4. The data processing device of claim 1, wherein the back-end circuit includes:

a combiner coupled to the first front-end circuit and configured to combine the first demodulated data and the second demodulated data to generate combined data; and

a decoder coupled to the combiner and configured to decode the combined data.

5. The data processing device of claim 4, wherein the combiner is further configured to synchronize the first demodulated data and the second demodulated data.

6. The data processing device of claim 5, wherein the combiner is further configured to:

obtain a synchronization marker from the second demodulated data, and

synchronize the first demodulated data and the second demodulated data based on the synchronization marker.

7. The data processing device of claim 1, wherein the transmitter is further configured to pack the second demodulated data into data packets and transmit the data packets to the first circuit.

8. The data processing device of claim 7, wherein the transmitter is further configured to add a synchronization marker to a packet head of one of the data packets.

9. The data processing device of claim 8, wherein the data packets include Orthogonal Frequency Division Multiplexing (OFDM) symbols containing the second demodulated data.

10. The data processing device of claim 9, wherein:

the OFDM symbols are grouped into at least one data subframe, and

the synchronization marker includes at least one of a subframe number or an OFDM symbol label.

11. The data processing device of claim 7, wherein the second circuit is further configured to:

transmit the data packets to a storage medium of the first circuit, and

send a write-complete indication to the first circuit after transmitting one of the data packets to the storage medium.

12. The data processing device of claim 11, wherein the first circuit is configured to send a read-complete indication to the second circuit after the back-end circuit reads the one of the data packets from the storage medium.

13. The data processing device of claim 11, further comprising:

a data link between the transmitter and the storage medium,

wherein the transmitter is configured to transmit the data packets through the data link,

14. The data processing device of claim 13, further comprising:

an instruction link between the first circuit and the second circuit, the instruction link being different from the data link,

wherein;

the second circuit is configured to send the write-complete indication to the first circuit through the instruction link, and

the first circuit is configured to send the read-complete indication to the second circuit through the instruction link.

15. The data processing device of claim 1, further comprising:

one or more first antennas coupled to the first front-end circuit and configured to receive wireless signals, convert the received wireless signals to the first data, and send the first data to the first front-end circuit; and

one or more second antennas coupled to the second front-end circuit and configured to receive the wireless signals, convert the received wireless signals to the second data, and send the second data to the second front-end circuit.

16. The data processing device of claim 15, wherein:

the first front-end circuit includes;

a first pre-circuit configured to pre-process the first data from the one or more first antenna to generate first pre-processed data; and

a first demodulator coupled to the first pre-circuit and configured to demodulate the first pre-processed data to generate the first demodulated data, and the second front-end circuit includes;

a second pre-circuit configured to pre-process the second data from the one or more second antennas to generate second pre-processed data; and

a second demodulator coupled to the second pre-circuit and configured to demodulate the second pre-processed data to generate the second demodulated data.

17. The data processing device of claim 16, wherein:

the first pre-circuit includes;

a first signal circuit configured to perform at least one of filtering, adjustment, analog-to-digital (AD) conversion, or sampling on the first data;

a first fast Fourier transformer (FFT'"'"'er) coupled to the first signal circuit and configured to perform fast Fourier transform (FFT) on the first data processed by the first signal circuit; and

a first channel estimator coupled between the first FFT'"'"'er and the first demodulator, and configured to perform a first channel estimation to obtain a first channel value for demodulating the first data, and

the second pre-circuit includes;

a second signal circuit configured to perform at least one of filtering, adjustment, analog-to-digital (AD) conversion, or sampling on the second data;

a second FFT'"'"'er coupled to the second signal circuit and configured to perform FFT on the second data processed by the second signal circuit; and

a second channel estimator coupled between the second FFT'"'"'er and the second demodulator, and configured to perform a second channel estimation to obtain a second channel value for demodulating the second data.

18. The data processing device of claim 1, wherein the first circuit is integrated in a first chip and the second processing circuit is integrated in a second chip.

19. A data processing method comprising:

processing, by a first circuit, first data to obtain first demodulated data;

processing, by a second circuit, second data to obtain second demodulated data;

transmitting, by the second circuit, the second demodulated data to the first circuit; and

processing, by the first circuit, the first demodulated data and the second demodulated data.

20. The data processing method of claim 19, wherein processing the first demodulated data and the second demodulated data includes:

combining the first demodulated data and the second demodulated data to generate combined data; and

decoding the combined data.