Apparatus for Dynamic Range Enhancement

• US 20200137327A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Dialog Semiconductor UK Ltd (Renesas Electronics Corporation)
• Original Assignee: Dialog Semiconductor UK Ltd (Renesas Electronics Corporation)
• Inventors: Hamilton, Joseph, Fijalkowski, Fryderyk
• Granted Patent: US 10,863,117 B2
• Time in Patent Office: Days
• CPC Class Codes: H03M 1/70 Automatic control for modifying converter range
• CPC Class Codes: H03M 3/344 by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
• CPC Class Codes: H03M 3/484 by adapting the gain of the feedback signal, e.g. by adapting the reference values of the digital/analogue converter in the feedback path
• CPC Class Codes: H03M 3/50 Digital/analogue converters using delta-sigma modulation as an intermediate step digital delta-sigma modulators per se H03M7/3004
• CPC Class Codes: H03M 3/51 Automatic control for modifying converter range
• CPC Class Codes: H03M 7/3026 the quantiser being a multiple bit one
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/60 Noise processing, e.g. detecting, correcting, reducing or removing noise

Abstract

An apparatus for dynamic range enhancement (DRE) which receives an input signal and provides a DRE output signal is presented. The apparatus has an error correction circuit to apply an error correction factor to the input signal such that the DRE output signal provided by the apparatus is dependent on the input signal and the error correction factor. The error correction factor is representative of an error generated by the apparatus.

Claims

1. An apparatus for dynamic range enhancement (DRE) which receives an input signal and provides a DRE output signal, comprising:

an error correction circuit configured to apply an error correction factor to the input signal such that the DRE output signal provided by the apparatus is dependent on the input signal and the error correction factor;

wherein;

the error correction factor is representative of an error generated by the apparatus.

2. The apparatus of claim 1, comprising:

a DRE circuit;

wherein;

the error correction circuit is configured to receive the input signal and to provide a corrected signal based on the input signal and the error correction factor; and

the DRE circuit is configured to receive the corrected signal and to provide the DRE output signal based on the received corrected signal.

3. The apparatus of claim 2, wherein the DRE circuit comprises:

an amplifier circuit configured to amplify the corrected signal;

a processing circuit configured to receive the corrected signal from the amplifier circuit and to process the corrected signal; and

an attenuation circuit configured to receive the corrected signal from the processing circuit, to attenuate the corrected signal and to provide the corrected signal as an output of the attenuation circuit;

wherein;

the DRE output signal corresponds to the corrected signal output by the attenuation circuit.

4. The apparatus of claim 3, wherein the processing circuit comprises:

a digital to analog converter (DAC) configured to receive the corrected signal from the amplifier circuit, wherein processing the corrected signal comprises converting the corrected signal from digital to analog using the DAC.

5. The apparatus of claim 3, wherein the error correction circuit comprises a summing circuit configured to generate the corrected signal by adding or subtracting the error correction factor from the input signal, the corrected signal being provided at an output of the error correction circuit.

6. The apparatus of claim 5, comprising a sigma delta modulator comprising the error correction circuit, wherein the sigma delta modulator is configured to reduce the resolution of the corrected signal prior to the corrected signal being received by the processing circuit.

7. The apparatus of claim 6, wherein the sigma delta modulator comprises:

a loop filter; and

a quantiser configured to reduce the resolution of the corrected signal prior to the corrected signal being received by the processing circuit;

wherein;

the loop filter comprises a first input for receiving the corrected signal and an output coupled to the quantiser; and

the quantiser has an output coupled to the processing circuit and a second input of the loop filter.

8. The apparatus of claim 7, wherein the output of the quantiser is coupled to the processing circuit via the amplifier circuit.

9. The apparatus of claim 7, wherein the loop filter is coupled to the quantiser via the amplifier circuit and the output of the quantiser is coupled to the second input the loop filter via a second amplifier circuit.

10. The apparatus of claim 3, comprising a sigma delta modulator comprising the error correction circuit, wherein the sigma delta modulator is configured to reduce the resolution of the corrected signal prior to the corrected signal being received by the processing circuit.

11. The apparatus of claim 10, wherein:

the error correction circuit comprises;

a loop filter comprising a first input for receiving the input signal; and

a summing circuit comprising a first input for receiving the error correction factor and an output coupled to the second input of the loop filter; and

the sigma delta modulator comprises;

a quantiser;

wherein;

the loop filter comprises an output coupled to the quantiser, wherein the corrected signal is provided at the output of the loop filter; and

the quantiser has an output coupled to the processing circuit and a second input of the summing circuit.

12. The apparatus of claim 11, wherein the output of the quantiser is coupled to the processing circuit via the amplifier circuit.

13. The apparatus of claim 11, wherein the loop filter is coupled to the quantiser via the amplifier circuit and the output of the quantiser is coupled to the second input of the loop filter via a second amplifier circuit.

14. The apparatus of claim 1, comprising a memory element configured to store the error correction factor and to provide the error correction factor to the error correction circuit.

15. The apparatus of claim 1, wherein the error correction factor is derived by calculating the error generated by the apparatus.

16. The apparatus of claim 1, comprising an error correction factor generator configured to:

detect the error generated by the apparatus;

to generate the error correction factor using the detected error; and

to provide the error correction factor to error correction circuit.

17. The apparatus of claim 1, wherein the apparatus comprises a DRE circuit comprising:

the error correction circuit;

an amplifier circuit configured to amplify the input signal;

a processing circuit configured to receive the input signal from the amplifier circuit and to process the input signal; and

an attenuation circuit configured to receive the input signal from the processing circuit, to attenuate the input signal and to provide the input signal as an output of the attenuation circuit;

wherein;

the DRE output signal corresponds to the input signal output by the attenuation circuit; and

the input signal is adjusted by the error correction circuit based on the error correction factor prior to being output by the attenuation circuit as the DRE output signal.

18. The apparatus of claim 17, wherein:

the attenuation circuit comprises the error correction circuit; and

the error correction circuit is configured to adjust the attenuation applied by the attenuation circuit based on the error correction factor.

19. The apparatus of claim 1, wherein the error generated by the apparatus results from at least one of a gain change or a delay.

20. The apparatus of claim 1, wherein the error correction circuit is configured to receive the error correction factor.

21. A method of dynamic range enhancement (DRE) using an apparatus comprising an error correction circuit, the method comprising the steps of:

receiving an input signal at the apparatus;

applying an error correction factor to the input signal using the error correction circuit; and

providing a DRE output signal;

wherein;

the DRE output signal provided by the apparatus is dependent on the input signal and the error correction factor; and

;

the error correction factor is representative of an error generated by the apparatus.