SIMULTANEOUS MULTIPLE WELL SIZE INTEGRATION

• US 20200137329A1
• Filed: 07/18/2017
• Published: 04/30/2020
• Est. Priority Date: 07/18/2017
• Status: Active Grant

• Current Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Original Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Inventors: Hairston, Allen W.
• Granted Patent: US 10,623,670 B1
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

An integration circuit having multiple wells that allow for the simultaneous storage of charge during an integration interval and techniques for using the same provide benefits in dynamic range that enhance the performance of pixels. The circuit and techniques described herein could also be used in many different infrared focal plane array applications where higher dynamic range is desired and multiple gain state outputs are allowed.

Claims

1. An integration circuit, the integration circuit comprising:

an input configured to carry an input current;

a first well comprising an input, an output, and a first integration capacitor configured to collect the input current, wherein a first well voltage changes proportionally to the input current over an integration time;

a second well comprising an input, an output, and a second integration capacitor configured to collect the input current, wherein a second well voltage changes proportionally to the input current over an integration time and wherein said second well input begins to collect a charge from the input current when the first well voltage approaches a predetermined level;

a reset switch electrically connected between the input and output of said second well;

a gain control transistor electrically connected between the output of said second well and the output of said first well and configured to allow charge to be integrated on said second well when the first well is full;

a first sampling switch electrically connected to the first well;

a first voltage-measuring device electrically connected to said first sampling switch, such that charge flows through said first sampling switch into said first voltage-measuring device upon closure of said first sampling switch;

a second sampling switch electrically connected to said first well; and

a second voltage-measuring device electrically connected to said second sampling switch, such that charge flows through said second sampling switch into said second voltage-measuring device upon closure of said second sampling switch.

2. The integration circuit of claim 1 further comprising an amplifier with capacitive feedback electrically connected between the inputs and outputs of said first and second wells.

3. The integration circuit of claim 1 further comprising a bias control transistor having a source, a gate, and a drain, wherein said source is connected to the input, said gate is connected to a bias control voltage and said drain is connected to the output of said first and second integration capacitors.

4. The integration circuit of claim 3 further comprising an inverting amplifier connected between the source and gate of said bias control transistor.

5. The integration circuit of claim 1 further comprising one or more additional integration wells, each additional well having an additional corresponding gain control FET, sampling switch and voltage measuring device, thereby allowing more than two gain states.

6. A pixel comprising the integration circuit of claim 1.

7. An integration circuit, the integration circuit comprising:

an operational amplifier comprising a non-inverting positive input, a non-inverting negative input, and an output;

a first well having an input and an output, wherein said first well input is electrically connected to the inverting negative input of said operational amplifier and said first well output is electrically connected to the output of said operational amplifier;

a second well having an input and an output, wherein said second well input is electrically connected the non-inverting negative input of said operational amplifier and said second well output is electrically connected to the output of said operational amplifier, wherein said first well and said second well are connected in parallel;

a reset switch electrically connected between the input and output of said second well;

a gain control switch electrically connected between the output of said second well and the output of said first well;

a first sampling switch electrically connected to the output of said operational amplifier;

a first charge-measuring device electrically connected to said first sampling switch, such that charge flows through the first sampling switch into the first charge-measuring device upon closure of the first sampling switch;

a second sampling switch electrically connected to the output of said operational amplifier; and

a second charge-measuring device electrically connected to said second sampling switch, such that charge flows through the second sampling switch into the second charge-measuring device upon closure of the second sampling switch.

8. The integration circuit of claim 7 wherein said second well is of a relatively lower gain compared to said first well.

9. The integration circuit of claim 7 wherein said gain control switch is a field effect transistor having a source, a drain, and a gate, wherein said source and drain are connected between the outputs of said first and second wells and said gate is electrically connected to a source of voltage proportional to a charge on said first well, wherein said gate is configured to allow charge to flow between said drain and source upon a threshold voltage indicative of said first well nearing saturation, thereby allowing charge to flow to said second well.

10. The integration circuit of claim 9 wherein said field effect transistor is an n-type field effect transistor.

11. The integration circuit of claim 10 wherein said drain is electrically connected to said output of said second well, said source is electrically connected to said output of said first well.

12. The integration circuit of claim 7 wherein each well comprises at least one capacitor.

13. The integration circuit of claim 7 further comprising a detector diode electrically connected to the inverting negative input of said operational amplifier.

14. The integration circuit of claim 7 further comprising one or more additional integration wells, each additional well having an additional corresponding gain control FET, sampling switch and voltage measuring device, thereby allowing more than two gain states.

15. A pixel comprising the integration circuit of claim 7.

16. A method of operating an integration circuit, the method comprising:

on an integration circuit comprising;

an operational amplifier comprising a non-inverting positive input, a non-inverting negative input, and an output;

a first well having an input and an output, wherein said first well input is electrically connected to the inverting negative input of said operational amplifier and said first well output is electrically connected to the output of said operational amplifier;

a second well having an input and an output, wherein said second well input is electrically connected the non-inverting negative input of said operational amplifier and said second well output is electrically connected to the output of said operational amplifier, wherein said first well and said second well are connected in parallel;

a reset switch electrically connected between the input and output of said second well;

a gain control field effect transistor having a source, a drain, and a gate, wherein said source and drain are connected between the outputs of said first and second wells and said gate is electrically connected to a source of voltage proportional to a charge on said first well, wherein said gate is configured to allow charge to flow between said drain and source upon a threshold voltage indicative of said first well nearing saturation, thereby allowing charge to flow to said second well;

a first sampling switch electrically connected to the output of said operational amplifier;

a first charge-measuring device electrically connected to said first sampling switch, such that charge flows through the first sampling switch into the first charge-measuring device upon closure of the first sampling switch;

a second sampling switch electrically connected to the output of said operational amplifier; and

a second charge-measuring device electrically connected to said second sampling switch, such that charge flows through the second sampling switch into the second charge-measuring device upon closure of the second sampling switch;

wherein said integration circuit is electrically connected to a source of current to be measured over an integration interval;

integrating a current over an integration interval by;

applying a voltage in excess of the threshold voltage to the gain control field effect transistor, thereby enabling current to flow between the source and drain thereof;

closing the reset switch, thereby resetting said first and second wells;

removing said voltage from said gate of said gain control field effect transistor;

opening said reset switch, thereby allowing charge to build on said first well;

wherein, if said first well approaches saturation charge flows through said gain control field effect transistor, allowing integration to continue on said second well;

sampling said first well by disconnecting said threshold voltage from said gate of said gain control field effect transistor, if a threshold voltage was applied during the integration interval, and closing said first sampling switch, thereby allowing charge from said first well to flow into said first charge measuring device; and

if a threshold voltage was applied to the gate of said gain control field effect transistor during the integration interval, opening said second sampling switch and applying a threshold voltage to said gate of said gain control field effect transistor, thereby allowing charge to equalize between said first and second wells and to flow into said second charge-measuring device.

17. The method of operating an integration circuit of claim 16 wherein said first well is of a relatively higher-gain.

18. The method of operating an integration circuit of claim 16 wherein a voltage above the threshold voltage is applied to the gate of said gain control field effect transistor following an integration interval regardless of whether or not the first well was saturated, allowing charge to be fully shared across said first and second wells, prior to sampling, allowing for charge measurement on either the first or second charge measuring device whether or not the first well was saturated during the integration interval.

19. The method of operating an integration circuit of claim 16 wherein the charge transferred to said first and second charge-measuring devices is read out during a subsequent integration.

20. The method of operating an integration circuit of claim 19 wherein said charge is read out of said first and second charge-measuring devices by a readout integrated circuit.