SENSOR PIXEL AND IMAGE SENSORS COMPRISING THE SAME

• US 20200137337A1
• Filed: 10/14/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Abandoned Application

• Current Assignee: Silicon Display Technology
• Original Assignee: Silicon Display Technology
• Inventors: JIN, Jong Woo, Yu, Jinhyeong, Hong, Sung Soo, Park, Young Man, Go, Taehan, Choi, Soon Ho, Nam, Youn Duck
• Application Number:
  US16/600,640
• Publication Number:
  US 20200137337A1
• Time in Patent Office: Days
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/531 by controlling rolling shutters in CMOS SSIS
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/7795 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

The present invention relates to a sensor pixel including: a first transistor for a light sensing; a second transistor including one terminal connected to one terminal of the first transistor and the other terminal to which a reset voltage is transmitted; a third transistor including a gate connected to one terminal of the first transistor and one terminal connected to the other terminal of the first transistor; and a fourth transistor connected between the other terminal of the third transistor and a data line.

Claims

1. A sensor pixel comprising:

a first transistor for light sensing;

a second transistor including one terminal connected to one terminal of the first transistor and the other terminal to which a reset voltage is transmitted;

a third transistor including a gate connected to one terminal of the first transistor and one terminal connected to the other terminal of the first transistor; and

a fourth transistor connected between the other terminal of the third transistor and a data line.

2. The sensor pixel of claim 1, wherein

the first transistor is formed of amorphous silicon.

3. The sensor pixel of claim 1, further comprising

a capacitor for fixing a gate voltage of the third transistor.

4. The sensor pixel of claim 3, wherein

the capacitor includes

a parasitic capacitor of the third transistor, a first capacitor formed between a gate and one terminal of the third transistor, a second capacitor formed between the gate of the third transistor and the gate of the first transistor, a third capacitor formed between the gate of the third transistor and the other terminal of the second transistor, or at least two among the parasitic capacitor and the first to third capacitors.

5. The sensor pixel of claim 1, wherein

the fourth transistor is switched depending on a first gate signal, the second transistor is switched depending to a second gate signal, and enable timing of the second gate signal precedes enable timing of the first gate signal.

6. An image sensor comprising:

a sensor panel including a plurality of sensor pixels, and a plurality of first gate lines, a plurality of second gate lines, and a plurality of data lines connected to the plurality of sensor pixels;

a gate driving circuit supplying a plurality of first gate signals and a plurality of second gate signals corresponding to the plurality of first gate lines and the plurality of second gate lines; and

a sensor signal readout circuit receiving a plurality of data signals from the plurality of sensor pixels through the plurality of data lines,

wherein each of the plurality of pixel sensors is implemented by a sensor pixel,

wherein the sensor pixel comprises;

a first transistor for light sensing;

a second transistor including one terminal connected to one terminal of the first transistor and the other terminal to which a reset voltage is transmitted;

a third transistor including a gate connected to one terminal of the first transistor and one terminal connected to the other terminal of the first transistor; and

a fourth transistor connected between the other terminal of the third transistor and a data line.

7. The image sensor of claim 6, wherein

a phase difference exists between the first gate signal and the second gate signal corresponding to the plurality of sensor pixels disposed in the same row.

8. The image sensor of claim 7, wherein

the enable timing of the second gate signal precedes the enable timing of the first gate signal.

9. The image sensor of claim 6, wherein

the gate driving circuit includes:

a first gate driving unit generating a plurality of first gate signals; and

a second gate driving unit generating a plurality of second gate signals.