VIDEO CODING WITH TRADE-OFF BETWEEN FRAME RATE AND CHROMA FIDELITY
1. A method comprising:
- receiving a compressed input video stream having a first display resolution and encoded in a first format employing a first combination of frame rate and chroma fidelity; and
decompressing the compressed input video stream to generate an output video stream having a second format, the second format having the first display resolution and a different second combination of frame rate and chroma fidelity.
A video decoder or encoder can be used to convert and process different video streams having different combinations of frame rate and Chroma fidelity. Rather than setting the maximum sample rate of the encoder based on a Luma sample rate, the encoder'"'"'s throughput is set based on a maximum color sample rate. Additionally, the picture buffer size can be set based on a maximum number of color pictures. An input of the video decoder receives an input video stream having a given display resolution and encoded in a first format employing a first combination of frame rate and Chroma fidelity. Processing circuitry in the decoder converts the input video stream from the first format to an output video stream having a second format, the second format having the given display resolution and employing a second combination of frame rate and Chroma fidelity different from the first combination.
- 1. A method comprising:
receiving a compressed input video stream having a first display resolution and encoded in a first format employing a first combination of frame rate and chroma fidelity; and decompressing the compressed input video stream to generate an output video stream having a second format, the second format having the first display resolution and a different second combination of frame rate and chroma fidelity.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15)
- 10. A video decoder comprising:
an input configured to receive a compressed input video stream having a display resolution and encoded in a first format employing a first combination of frame rate and chroma fidelity; and a processor and associated memory configured to decompress the compressed input video stream to generate an output video stream having a second format, the second format having the same display resolution, but a different combination of frame rate and chroma fidelity.
- 16. A video decoder comprising:
an input configured to receive a compressed input video stream having a display resolution and encoded in a first format employing a first combination of frame rate and Chroma fidelity; and processing circuitry configured to decompress the compressed input video stream to generate an output video stream having a second format, the second format having the same display resolution, but a different combination of frame rate and chroma fidelity, the processing circuitry including; an entropy decoder coupled to the input and configured to generate quantized transform coefficients, intra prediction modes, motion data, and filter parameters; a reconstruction circuit configured to generate currently reconstructed pictures by summing residual blocks and at least one of intra prediction blocks, inter prediction blocks, or motion-compensated prediction blocks; and a picture buffer configured to store reference pictures and the currently reconstructed pictures during video decoding, and having a maximum capacity determined by a maximum number of color pictures.
- View Dependent Claims (17, 18, 19, 20)
The present U.S. Utility Patent Application claims priority pursuant to 35 U.S.C. § 120 as a divisional of U.S. Utility application Ser. No. 15/242,742, entitled “VIDEO CODING WITH TRADE-OFF BETWEEN FRAME RATE AND CHROMA,” filed Aug. 22, 2016 and pending, which claims priority pursuant to 35 U.S.C. § 119(e) to U.S. Provisional Application No. 62/216,066, entitled “VIDEO CODING WITH TRADE-OFF BETWEEN FRAME RATE AND CHROMA FIDELITY,” filed Sep. 9, 2015, and U.S. Provisional Application No. 62/372,960, entitled “VIDEO CODING WITH TRADE-OFF BETWEEN FRAME RATE AND CHROMA FIDELITY,” filed Aug. 10, 2016, which are incorporated herein by reference in their entirety, and made part of the present U.S. Utility Patent Application for all purposes.
The invention relates generally to digital video processing; and, more particularly, it relates to processing and operations in accordance with such digital video processing.
Communication systems that operate to communicate digital media (e.g., images, video, data, etc.) have been under continual development for many years. With respect to such communication systems employing some form of video data, a number of digital images are output or displayed at some frame rate (e.g., frames per second) to effectuate a video signal suitable for output and consumption. Within many such communication systems operating using video data, there can be a trade-off between throughput (e.g., number of image frames that may be transmitted from a first location to a second location) and video and/or image quality of the signal eventually to be output or displayed.
Profile and level specification is often used in a video compression standard to constrain video decoder complexity. A profile specifies a selected set of coding tools for a compliant decoder to implement, while a level constrains the decoder cost in terms of maximum bit-rate, maximum sample rate, maximum decoder picture buffer size, maximum luminance picture size, etc. Current technology lacks the flexibility to allow a system to deliver the best possible video quality by making the most efficient use of decoder resources.
In various embodiments described herein, a decoder can repurpose its memory usage usage and pixel processing capability based on the video format, including Chroma-format and frame-rate, of an incoming bitstream. Thus, in some embodiments, a decoder can support 4:2:0 streams with doubled maximum frame-rate and number of reference pictures.
For example, a decoder can decode a bitstream encoded in a first format and output video in the first format, e.g. in 4:2:0, and also decode a bitstream encoded in a second format, e.g. in 4:4:4, but the video output in 4:2:0 format is allowed to have doubled maximum frame-rate and number of reference pictures as compared to the video output in 4:4:4 format. That is to say, the decoder can trade decreased Chroma fidelity with frame-rate and number of reference pictures, but still use the same amount of processing and memory resources.
An encoder can similarly exercise a tradeoff between Chroma fidelity and frame-rate. For example, if an input video signal to the video encoder is 4:4:4@60 fps, but a compliant bitstream is limited to being encoded as 4:4:4@30 fps, various encoders described herein can choose whether to encode the incoming video, for as 4:4:4@30 fps with up to, for example, 5 reference pictures, or as 4:2:0@60 fps with up to, for example, 10 reference pictures for the same memory footprint, memory bandwidth and pixel processing speed.
Also, according to various embodiments, a transmitted bitstream created by an embodiment of an encoder and decoded by an embodiment of a decoder, supports such a trade-off between Chroma fidelity and frame-rate. Thus, in some implementations, a compliant bitstream can include a steam of the first format only, the second format only, or a mixed stream including portions encoded in both the first and second formats, where the first format may have a higher maximum allowable frame-rate and number of reference pictures, but a lower Chroma-fidelity, while the second format may have a higher Chroma fidelity but a lower allowable maximum frame-rate and number of reference pictures.
Within many devices that use digital media such as digital video, respective images thereof, being digital in nature, are represented using pixels. Within certain communication systems, digital media can be transmitted from a first location to a second location at which such media can be output or displayed. The goal of digital communications systems, including those that operate to communicate digital video, is to transmit digital data from one location, or subsystem, to another either error free or with an acceptably low error rate. As shown in
It is noted that such communication devices 110 and/or 120 may be stationary or mobile without departing from the scope and spirit of the invention. For example, either one or both of the communication devices 110 and 120 may be implemented in a fixed location or may be a mobile communication device with capability to associate with and/or communicate with more than one network access point (e.g., different respective access points (APs) in the context of a mobile communication system including one or more wireless local area networks (WLANs), different respective satellites in the context of a mobile communication system including one or more satellite, or generally, different respective network access points in the context of a mobile communication system including one or more network access points by which communications may be effectuated with communication devices 110 and/or 120.
To reduce transmission errors that may undesirably be incurred within a communication system, error correction and channel coding schemes are often employed. Generally, these error correction and channel coding schemes involve the use of an encoder at the transmitter end of the communication channel 199 and a decoder at the receiver end of the communication channel 199.
Any of various types of ECC codes described can be employed within any such desired communication system (e.g., including those variations described with respect to
Generally speaking, when considering a communication system in which video data is communicated from one location, or subsystem, to another, video data encoding may generally be viewed as being performed at a transmitting end of the communication channel 199, and video data decoding may generally be viewed as being performed at a receiving end of the communication channel 199.
Also, while the embodiment of this diagram shows bi-directional communication being capable between the communication devices 110 and 120, it is of course noted that, in some embodiments, the communication device 110 may include only video data encoding capability, and the communication device 120 may include only video data decoding capability, or vice versa (e.g., in a uni-directional embodiment such as in accordance with a video broadcast embodiment).
Referring to the communication system 200 of
Within each of the transmitter 297 and the receiver 298, any desired integration of various components, blocks, functional blocks, circuitries, etc. Therein may be implemented. For example, this diagram shows a processing module 280a as including the encoder and symbol mapper 220 and all associated, corresponding components therein, and a decoder 280 is shown as including the metric generator 270 and the decoder 280 and all associated, corresponding components therein. Such processing modules 280a and 280b may be respective integrated circuits. Of course, other boundaries and groupings may alternatively be performed without departing from the scope and spirit of the invention. For example, all components within the transmitter 297 may be included within a first processing module or integrated circuit, and all components within the receiver 298 may be included within a second processing module or integrated circuit. Alternatively, any other combination of components within each of the transmitter 297 and the receiver 298 may be made in other embodiments.
As with the previous embodiment, such a communication system 200 may be employed for the communication of video data is communicated from one location, or subsystem, to another (e.g., from transmitter 297 to the receiver 298 via the communication channel 299).
Digital image and/or video processing of digital images and/or media (including the respective images within a digital video signal) may be performed by any of the various devices depicted below in
Referring to embodiment 400 of
The input video signal may generally be referred to as corresponding to raw frame (or picture) image data. For example, raw frame (or picture) image data may undergo processing to generate luma and Chroma samples. In some embodiments, the set of luma samples in a macro-block is of one particular arrangement (e.g., 16×16), and set of the Chroma samples is of a different particular arrangement (e.g., 8×8). In accordance with the embodiment depicted herein, a video encoder processes such samples on a block by block basis.
The input video signal then undergoes mode selection by which the input video signal selectively undergoes intra and/or inter-prediction processing. Generally speaking, the input video signal undergoes compression along a compression pathway. When operating with no feedback (e.g., in accordance with neither inter-prediction nor intra-prediction), the input video signal is provided via the compression pathway to undergo transform operations (e.g., in accordance with discrete cosine transform (DCT)). Of course, other transforms may be employed in alternative embodiments. In this mode of operation, the input video signal itself is that which is compressed. The compression pathway may take advantage of the lack of high frequency sensitivity of human eyes in performing the compression.
However, feedback may be employed along the compression pathway by selectively using inter- or intra-prediction video encoding. In accordance with a feedback or predictive mode of operation, the compression pathway operates on a (relatively low energy) residual (e.g., a difference) resulting from subtraction of a predicted value of a current macro-block from the current macro-block. Depending upon which form of prediction is employed in a given instance, a residual or difference between a current macro-block and a predicted value of that macro-block based on at least a portion of that same frame (or picture) or on at least a portion of at least one other frame (or picture) is generated.
The resulting modified video signal then undergoes transform operations along the compression pathway. In one embodiment, a discrete cosine transform (DCT) operates on a set of video samples (e.g., luma, Chroma, residual, etc.) to compute respective coefficient values for each of a predetermined number of basis patterns. For example, one embodiment includes 64 basis functions (e.g., such as for an 8×8 sample). Generally speaking, different embodiments may employ different numbers of basis functions (e.g., different transforms). Any combination of those respective basis functions, including appropriate and selective weighting thereof, may be used to represent a given set of video samples. Additional details related to various ways of performing transform operations are described in the technical literature associated with video encoding including those standards/draft standards that have been incorporated by reference as indicated above. The output from the transform processing includes such respective coefficient values. This output is provided to a quantizer.
Generally, most image blocks will typically yield coefficients (e.g., DCT coefficients in an embodiment operating in accordance with discrete cosine transform (DCT)) such that the most relevant DCT coefficients are of lower frequencies. Because of this and of the human eyes'"'"' relatively poor sensitivity to high frequency visual effects, a quantizer may be operable to convert most of the less relevant coefficients to a value of zero. That is to say, those coefficients whose relative contribution is below some predetermined value (e.g., some threshold) may be eliminated in accordance with the quantization process. A quantizer may also be operable to convert the significant coefficients into values that can be coded more efficiently than those that result from the transform process. For example, the quantization process may operate by dividing each respective coefficient by an integer value and discarding any remainder. Such a process, when operating on typical coding units or macro-blocks, typically yields a relatively low number of non-zero coefficients which are then delivered to an entropy encoder for lossless encoding and for use in accordance with a feedback path which may select intra-prediction and/or inter-prediction processing in accordance with video encoding.
An entropy encoder operates in accordance with a lossless compression encoding process. In comparison, the quantization operations are generally lossy. The entropy encoding process operates on the coefficients provided from the quantization process. Those coefficients may represent various characteristics (e.g., luma, Chroma, residual, etc.). Various types of encoding may be employed by an entropy encoder. For example, context-adaptive binary arithmetic coding (CABAC) and/or context-adaptive variable-length coding (CAVLC) may be performed by the entropy encoder. For example, in accordance with at least one part of an entropy coding scheme, the data is converted to a (run, level) pairing (e.g., data 14, 3, 0, 4, 0, 0, −3 would be converted to the respective (run, level) pairs of (0, 14), (0, 3), (1, 4), (2, −3)). In advance, a table may be prepared that assigns variable length codes for value pairs, such that relatively shorter length codes are assigned to relatively common value pairs, and relatively longer length codes are assigned for relatively less common value pairs.
As the reader will understand, the operations of inverse quantization and inverse transform correspond to those of quantization and transform, respectively. For example, in an embodiment in which a DCT is employed within the transform operations, then an inverse DCT (IDCT) is that employed within the inverse transform operations.
A picture buffer, alternatively referred to as a digital picture buffer or a DPB, receives the signal from the IDCT module; the picture buffer is operative to store the current frame (or picture) and/or one or more other frames (or pictures) such as may be used in accordance with intra-prediction and/or inter-prediction operations as may be performed in accordance with video encoding. It is noted that in accordance with intra-prediction, a relatively small amount of storage may be sufficient, in that, it may not be necessary to store the current frame (or picture) or any other frame (or picture) within the frame (or picture) sequence. Such stored information may be employed for performing motion compensation and/or motion estimation in the case of performing inter-prediction in accordance with video encoding.
In one possible embodiment, for motion estimation, a respective set of luma samples (e.g., 16×16) from a current frame (or picture) are compared to respective buffered counterparts in other frames (or pictures) within the frame (or picture) sequence (e.g., in accordance with inter-prediction). In one possible implementation, a closest matching area is located (e.g., prediction reference) and a vector offset (e.g., motion vector) is produced. In a single frame (or picture), a number of motion vectors may be found and not all will necessarily point in the same direction. One or more operations as performed in accordance with motion estimation are operative to generate one or more motion vectors.
Motion compensation is operative to employ one or more motion vectors as may be generated in accordance with motion estimation. A prediction reference set of samples is identified and delivered for subtraction from the original input video signal in an effort hopefully to yield a relatively (e.g., ideally, much) lower energy residual. If such operations do not result in a yielded lower energy residual, motion compensation need not necessarily be performed and the transform operations may merely operate on the original input video signal instead of on a residual (e.g., in accordance with an operational mode in which the input video signal is provided straight through to the transform operation, such that neither intra-prediction nor inter-prediction are performed), or intra-prediction may be utilized and transform operations performed on the residual resulting from intra-prediction. Also, if the motion estimation and/or motion compensation operations are successful, the motion vector may also be sent to the entropy encoder along with the corresponding residual'"'"'s coefficients for use in undergoing lossless entropy encoding.
The output from the overall video encoding operation is an output bit stream. It is noted that such an output bit stream may of course undergo certain processing in accordance with generating a continuous time signal which may be transmitted via a communication channel. For example, certain embodiments operate within wireless communication systems. In such an instance, an output bitstream may undergo appropriate digital to analog conversion, frequency conversion, scaling, filtering, modulation, symbol mapping, and/or any other operations within a wireless communication device that operate to generate a continuous time signal capable of being transmitted via a communication channel, etc.
Referring to embodiment 500 of
Referring to embodiment 600 of
It is noted that a corresponding video decoder, such as located within a device at another end of a communication channel, is operative to perform the complementary processes of decoding, inverse transform, and reconstruction to produce a respective decoded video sequence that is (ideally) representative of the input video signal.
In comparing this diagram to the pervious diagram, in which the signal path output from the inverse quantization and inverse transform (e.g., IDCT) block is provided to both the intra-prediction block and a de-blocking filter, the output from the de-blocking filter is provided to one or more other in-loop filters (e.g., implemented in accordance with adaptive loop filter (ALF), sample adaptive offset (SAO) filter, and/or any other filter type) implemented to process the output from the inverse transform block. For example, in one possible embodiment, a SAO filter is applied to the decoded picture before it is stored in a picture buffer (again, sometimes alternatively referred to as a DPB, digital picture buffer).
With respect to any video encoder architecture implemented to generate an output bitstream, it is noted that such architectures may be implemented within any of a variety of communication devices. The output bitstream may undergo additional processing including error correction code (ECC), forward error correction (FEC), etc. thereby generating a modified output bitstream having additional redundancy deal therein. Also, as may be understood with respect to such a digital signal, it may undergo any appropriate processing in accordance with generating a continuous time signal suitable for or appropriate for transmission via a communication channel. That is to say, such a video encoder architecture may be implemented within a communication device operative to perform transmission of one or more signals via one or more communication channels. Additional processing may be made on an output bitstream generated by such a video encoder architecture thereby generating a continuous time signal that may be launched into a communication channel.
The residual, which is the difference between the current pixel and the reference or prediction pixel, is that which gets encoded. As can be seen with respect to this diagram, intra-prediction operates using pixels within a common frame (or picture). It is of course noted that a given pixel may have different respective components associated therewith, and there may be different respective sets of samples for each respective component.
A residual may be calculated in accordance with inter-prediction processing, though such a residual is different from the residual calculated in accordance with intra-prediction processing. In accordance with inter-prediction processing, the residual at each pixel again corresponds to the difference between a current pixel and a predicted pixel value. However, in accordance with inter-prediction processing, the current pixel and the reference or prediction pixel are not located within the same frame (or picture). While this diagram shows inter-prediction as being employed with respect to one or more previous frames or pictures, it is also noted that alternative embodiments may operate using references corresponding to frames before and/or after a current frame. For example, in accordance with appropriate buffering and/or memory management, a number of frames may be stored. When operating on a given frame, references may be generated from other frames that precede and/or follow that given frame.
Coupled with the CU, a basic unit may be employed for the prediction partition mode, namely, the prediction unit, or PU. It is also noted that the PU is defined only for the last depth CU, and its respective size is limited to that of the CU.
Generally speaking, such video decoding architectures operate on an input bitstream. It is of course noted that such an input bitstream may be generated from a signal that is received by a communication device from a communication channel. Various operations may be performed on a continuous time signal received from the communication channel, including digital sampling, demodulation, scaling, filtering, etc. such as may be appropriate in accordance with generating the input bitstream. Moreover, certain embodiments, in which one or more types of error correction code (ECC), forward error correction (FEC), etc. may be implemented, may perform appropriate decoding in accordance with such ECC, FEC, etc. thereby generating the input bitstream. That is to say, in certain embodiments in which additional redundancy may have been made in accordance with generating a corresponding output bitstream (e.g., such as may be launched from a transmitter communication device or from the transmitter portion of a transceiver communication device), appropriate processing may be performed in accordance with generating the input bitstream. Overall, such a video decoding architectures and lamented to process the input bitstream thereby generating an output video signal corresponding to the original input video signal, as closely as possible and perfectly in an ideal case, for use in being output to one or more video display capable devices.
Referring to the embodiment 900 of
In an example of operation, an incoming compressed input bitstream is entropy (CABAC) decoded. The CABAC decoding block delivers information about quantized transform coefficients, intra prediction modes, motion data and filter parameters for the current coding unit (CU). The quantized transform coefficients go through the process of inverse quantization and inverse transform to derive the residual blocks for the CU. The intra prediction modes are fed into the intra prediction block to produce the intra prediction blocks for the current CU, and the motion data is input to the inter prediction block to produce the motion-compensated prediction blocks for the current CU. Depending on whether the CU is intra or inter-coded, the intra or inter prediction blocks are added to the residual blocks (i.e. inverse transform output) to form the reconstructed CU before in-loop filtering. Finally, the in-loop filtering (e.g. de-blocking filter and Sample Adaptive Offset (SAO)) is performed to obtain the final reconstructed CU.
The maximum bit-rate specified in a level defines the required CABAC throughput of a compliant decoder. The maximum sample rate defines the required throughput of the rest of function blocks (i.e. motion compensation, intra prediction, inverse quantization and inverse transform, de-blocking filter and SAO) in video decoder 1000. The maximum decoder picture buffer size defines the required memory size to buffer the reference pictures and the reconstructed picture; and the maximum luminance picture size defines the maximum picture size supported by the level.
In existing standards such as ISO/IEC MPEG HEVC/ITU-T H.265, ISO/IEC MPEG AVC/ITU-T H.264 and ISO/IEC MPEG2 ITU-T H.262, the maximum sample rate defined in a level is specified in terms of maximum luma sample rate. That is, for a 4:4:4 (Y:Cr:Cb) profile which may support not only 4:4:4 Chroma format, but also 4:2:0 and 4:2:2 Chroma-formats, the throughput requirement is the same in terms of number of luma pictures per second regardless of Chroma format. For example, in conventional standards, if a level specifies the maximum sample rate as UHD 2160p@30 (3840×2160 at 30 fps), then the required decoder sample throughput is always 30 fps for 2160p video, regardless of Chroma format (4:4:4, 4:2:2, 4:2:0).
The restriction discussed above may not be desirable in all video applications. It is well known that high frame rate (HFR) is advantageous to reducing motion blur in high-motion sequences such as sports programs, while using full-fidelity Chroma format 4:4:4 can avoid color down-sampling artifacts caused by reduced Chroma fidelity such as using Chroma format 4:2:0. Having the flexibility of configuring an encoder or decoder with different combinations of frame-rate and Chroma fidelity can lead to better video quality in video applications. For the example given the above, it would be advantageous to remove the restriction on sample throughput, so that a UHD 2160p@30 4:4:4 decoder can be repurposed as a UHD 2160p@60 4:2:0 decoder. Thus, according to various embodiments disclosed herein, the same decoder can deal with the mixed content (in terms of frame-rate and Chroma-format combinations) for the same amount of decoder resources. For instance, 2160p@30 4:4:4 mode can be used for non-high motion video scenes for better color fidelity, while 2160p@60 4:2:0 mode can be used for high motion sports scenes for better motion fidelity.
In general, the implementation cost of a video decoder mainly depends on the following factors:
Coding tools required to support that impact the logic area.
Maximum luma picture size that determines line buffer size.
Maximum bit-rate that determines required entropy (e.g. CABAC) decoding throughput.
Maximum sample rate that determines required sample throughput of the decoder.
Decoder picture buffer size that determines the memory size needed for buffering the reference pictures and currently reconstructed picture.
In at least one embodiment of the present disclosure, a level definition can be implemented that takes into account the Chroma format. The following changes to a level definition can be used according to various embodiments: 1) the maximum sample rate can be defined as the maximum color sample rate instead of maximum luma sample rate; and 2) the decoder picture buffer size (e.g. maxDpbPicBuf in HEVC spec) can be defined as number of color pictures. With these changes, it becomes possible to repurpose a high color fidelity decoder (e.g. a 4:4:4 profile decoder) to run at a higher frame-rate and use more number of reference pictures when it is configured to use a low Chroma format (e.g. 4:2:0, 4:2:2), thus enabling the quality trade-off between frame-rate and Chroma fidelity. Consider the following example.
Let MaxLumaPs (samples) be the maximum luma picture size, the maximum color sample rate (in terms of samples per second) is defined as:
Where cf=3 for Chroma format 4:4:4, 2 for Chroma format 4:2:2 and 1.5 for Chroma format 4:2:0, and MaxPicureRate is the maximum allowable picture rate when picture size is configured to the maximum picture size defined by MaxLumaPs.
For a level, the product of cf and MaxPicureRate is a constant, so that using different Chroma format yields different maximum allowable picture rate. For example, if using Chroma-format 4:4:4 leads to a maximum picture rate MaxPicureRate of 30 fps, then the maximum picture rate MaxPicureRate is 60 fps for Chroma-format 4:2:0.
Let maxDpbPicBuf be the maximum number of pictures that can be stored in the decoder picture buffer, the picture size here is configured to the maximum luma picture size (defined by MaxLumaPs), the size of decoder picture buffer (in terms of samples) is defined as
For a level, the product of cf and maxDpbPicBuf is a constant, so that using different Chroma format yields different number of pictures that can be buffered by decoder. For example, if using Chroma-format 4:4:4 leads to a value of maxDpbPicBuf of 6, then the value of maxDpbPicBuf is 12 for Chroma-format 4:2:0.
The proposed modifications in level definition enable use of trade-off between frame-rate and Chroma format for high color fidelity profile decoder such as a 4:4:4 profile decoder. For a same amount of decoder resource, i.e. memory bandwidth, decoder picture buffer size, on-chip line buffer size, CABAC entropy decoding speed (throughput), decoder sample process speed (throughput), the decoder can operate with different combinations of frame-rate and Chroma format (e.g. 2160p@30 4:4:4 vs. 2160p@60 4:2:0). With the proposed level specification, the following encoding and decoding structures and methods may be realized.
Referring next to
In some embodiments, the level definition can take into consideration the video bit-depth for the specification of maximum decoder picture buffer size and maximum sample rate. For example, a 10-bit 2160p@60 video decoder may be repurposed as an 8-bit 2160p video decoder of higher frame rate.
Method 1100 requires the least amount of encoder/decoder complexity increase since no reference picture buffer manipulation (i.e. reference picture up- or down-sampling, color space conversion, etc.) at video transition boundary is needed. It allows the maximum amount of coding flexibility. At the video transition boundary, not only frame rate and Chroma-format but also the luma picture size and color space can be different.
Referring next to
Referring next to
In some embodiments, the luma picture size is further restricted to be the same, then only the down- and up-sampling process of Chroma reference pictures needs to be specified (e.g. from 4:4:4 to 4:2:0, from 4:2:0 to 4:4:4, etc.). During the video transition from 4:4:4 to 4:2:0, the Chroma reference pictures in the decoder picture buffer of the 4:4:4 video segment needs to be down-sampled to create reference picture that 4:2:0 video can use. Similarly, during the video transition from 4:2:0 to 4:4:4, the Chroma reference pictures in the decoder picture buffer of the 4:2:0 video segment needs to be up-sampled to produce reference picture that 4:4:4 video can use. This is a relatively easy process because Chroma down- or up-sampling factor is restricted to be 2 in this particular example.
In other embodiments, luma picture size at transition boundary can be different. In this case, the down- and up-sampling process of both luma and Chroma reference pictures needs to be specified. In addition, the reference picture down- or up-sampling process of arbitrary ratio rather than fixed ratio should be specified.
Referring next to
In one of embodiments, the luma picture size is still restricted to be the same, then only the color space conversion (e.g. RGB to YCbCr, YCbCr to RGB, etc.) and the down- and up-sampling process of Chroma reference pictures (e.g. from 4:4:4 to 4:2:0, from 4:2:0 to 4:4:4, etc.) need to be specified. In
In other embodiments, luma picture size at transition boundary can be different. In addition to color space conversion of reference pictures, a luma/Chroma reference picture down- or up-sampling process of arbitrary ratio should be specified.
Different reference picture manipulation processes (i.e. color space conversion, reference picture up- and down-sampling) can be used in conjunction with methods 1300 and 1400. For example, conversion can be done on-the-fly block by block in some embodiments. Alternatively, picture-based conversion can be performed in advance, and the converted reference pictures can be pre-stored in decoder picture buffer.
In some embodiments, the video bit-depth can be different at the video transition boundary. In some such cases, the reference picture manipulation process would need to consider video bit-depths before and after the transition.
Referring next to
1. Perform optical-electro transfer function (OETF) to covert video from 4:4:4 linear RGB to non-linear 4:4:4 RGB.
2. If required video output format is non-4:4:4 YCbCr (e.g. 4:2:0), first convert video from non-linear RGB to 4:4:4 YCbCr format in reduced bit-depth (e.g. 10-bit), then down-sample video from Chroma format 4:4:4 to e.g. 4:2:0.
3. Otherwise, if required video output format is 4:4:4 YCbCr, convert video from non-linear RGB to 4:4:4 YCbCr format in reduced bit-depth (e.g. 10-bit).
4. Otherwise, if required video output format is 4:4:4 RGB convert video from non-linear RGB to non-linear 4:4:4 RGB format in reduced bit-depth (e.g. 10-bit).
Based on video characteristics the video pre-processing block may choose to convert the video in one of video formats (e.g. 2160p@30 4:4:4 RGB, 2160p@30 4:4:4 YCbCr or 2160p@60 4:2:0 YCbCr) and deliver it to the video encoder for compression.
The video encoder is designed in a way that it can take video of different formats (frame-rate, Chroma-format, RGB vs. YCbCr etc.) as input and compress the video according to a video standard such as ISO/IEC MPEG HEVC/ITU-T H.265. The compressed bitstream is packetized and transmitted to the receiver side.
On the receiver side, the video decoder is capable of taking a video bitstream of different formats (e.g. 2160p@30 4:4:4 RGB, 2160p@30 4:4:4 YCbCr or 2160p@60 4:2:0 YCbCr) as input and de-compressing it into one of video formats based on video format (frame-rate, Chroma-format, RGB vs. YCbCr etc.) signaled in the incoming bitstream. The decoded video is delivered to the video post-processing block for display processing. The interface between the video decoder and the video post-processing block could be HDMI (High-Definition Multimedia Interface).
In the video post-processing block, the following steps may be performed:
1. If the decoder output video Chroma format is non-4:4:4 (e.g. 4:2:0, 4:2:2) YCbCr, up-sample the Chroma to 4:4:4 YCbCr, then convert the resulting 4:4:4 YCbCr video to non-linear 4:4:4 RGB.
2. Otherwise, if the decoder output video Chroma format is 4:4:4 YCbCr, convert 4:4:4 YCbCr video to non-linear 4:4:4 RGB.
3. Otherwise, the decoder directly outputs video Chroma format in 4:4:4 non-linear RGB.
4. Perform electro-optical transfer function (EOTF) to covert video from non-linear 4:4:4 RGB to linear 4:4:4 RGB,
The video after video post processing is sent to display. Note that in this end to end system, the required resource (in terms of memory bandwidth, memory size, etc.) is the same for different video formats. For example, if the system supports 2160p@60 4:2:0 YCbCr, then no additional resource is needed for the system to support 2160p@30 4:4:4 RGB or YCbCr.
As may be used herein, the terms “substantially” and “approximately” provides an industry-accepted tolerance for its corresponding term and/or relativity between items. Such an industry-accepted tolerance ranges from less than one percent to fifty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. Such relativity between items ranges from a difference of a few percent to magnitude differences. As may also be used herein, the term(s) “operably coupled to”, “coupled to”, and/or “coupling” includes direct coupling between items and/or indirect coupling between items via an intervening item (e.g., an item includes, but is not limited to, a component, an element, a circuit, and/or a module) where, for indirect coupling, the intervening item does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As may further be used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as “coupled to”. As may even further be used herein, the term “operable to” or “operably coupled to” indicates that an item includes one or more of power connections, input(s), output(s), etc., to perform, when activated, one or more its corresponding functions and may further include inferred coupling to one or more other items. As may still further be used herein, the term “associated with”, includes direct and/or indirect coupling of separate items and/or one item being embedded within another item. As may be used herein, the term “compares favorably”, indicates that a comparison between two or more items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1.
As may also be used herein, the terms “processing module”, “module”, “processing circuit”, and/or “processing unit” (e.g., including various modules and/or circuitries such as may be operative, implemented, and/or for encoding, for decoding, for baseband processing, etc.) may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions. The processing module, module, processing circuit, and/or processing unit may have an associated memory and/or an integrated memory element, which may be a single memory device, a plurality of memory devices, and/or embedded circuitry of the processing module, module, processing circuit, and/or processing unit. Such a memory device may be a read-only memory (ROM), random access memory (RAM), volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processing module, module, processing circuit, and/or processing unit includes more than one processing device, the processing devices may be centrally located (e.g., directly coupled together via a wired and/or wireless bus structure) or may be distributedly located (e.g., cloud computing via indirect coupling via a local area network and/or a wide area network). Further note that if the processing module, module, processing circuit, and/or processing unit implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory element storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Still further note that, the memory element may store, and the processing module, module, processing circuit, and/or processing unit executes, hard coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the Figures. Such a memory device or memory element can be included in an article of manufacture.
The present invention has been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claimed invention. Further, the boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality. To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claimed invention. One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.
The present invention may have also been described, at least in part, in terms of one or more embodiments. An embodiment of the present invention is used herein to illustrate the present invention, an aspect thereof, a feature thereof, a concept thereof, and/or an example thereof. A physical embodiment of an apparatus, an article of manufacture, a machine, and/or of a process that embodies the present invention may include one or more of the aspects, features, concepts, examples, etc. described with reference to one or more of the embodiments discussed herein. Further, from figure to figure, the embodiments may incorporate the same or similarly named functions, steps, modules, etc. that may use the same or different reference numbers and, as such, the functions, steps, modules, etc. may be the same or similar functions, steps, modules, etc. or different ones.
Unless specifically stated to the contra, signals to, from, and/or between elements in a figure of any of the figures presented herein may be analog or digital, continuous time or discrete time, and single-ended or differential. For instance, if a signal path is shown as a single-ended path, it also represents a differential signal path. Similarly, if a signal path is shown as a differential path, it also represents a single-ended signal path. While one or more particular architectures are described herein, other architectures can likewise be implemented that use one or more data buses not expressly shown, direct connectivity between elements, and/or indirect coupling between other elements as recognized by one of average skill in the art.
The term “module” is used in the description of the various embodiments of the present invention. A module includes a functional block that is implemented via hardware to perform one or module functions such as the processing of one or more input signals to produce one or more output signals. The hardware that implements the module may itself operate in conjunction software, and/or firmware. As used herein, a module may contain one or more sub-modules that themselves are modules.
While particular combinations of various functions and features of the present invention have been expressly described herein, other combinations of these features and functions are likewise possible. The present invention is not limited by the particular examples disclosed herein and expressly incorporates these other combinations.