METHOD AND SYSTEM FOR LINK SYNCHRONIZATION IN AN LTE-TDD ARCHITECTURE

• US 20200137709A1
• Filed: 09/06/2019
• Published: 04/30/2020
• Est. Priority Date: 04/03/2015
• Status: Active Grant

• Current Assignee: Dali Systems Co., Ltd.
• Original Assignee: Dali Systems Co., Ltd.
• Inventors: Kim, Wan-Jong, Stapleton, Shawn Patrick
• Granted Patent: US 10,863,470 B2
• Time in Patent Office: Days
• CPC Class Codes: H04B 17/318 Received signal strength
• CPC Class Codes: H04B 7/04 using two or more spaced independent antennas
• CPC Class Codes: H04L 25/03 Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
• CPC Class Codes: H04L 27/2656 Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
• CPC Class Codes: H04L 27/2675 Pilot or known symbols
• CPC Class Codes: H04L 5/0048 Allocation of pilot signals, i.e. of signals known to the receiver
• CPC Class Codes: H04L 5/0053 Allocation of signaling, i.e. of overhead other than pilot signals
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04L 5/1469 using time-sharing
• CPC Class Codes: H04W 56/00 Synchronisation arrangements
• CPC Class Codes: H04W 56/001 Synchronization between nodes
• CPC Class Codes: H04W 56/0095 estimated based on signal strength
• CPC Class Codes: H04W 88/085 Access point devices with remote components

Abstract

A method of detecting a synchronization switching pulse using a power detector in a time division duplexing (TDD) system includes receiving an input signal, detecting a power level associated with the input signal using a digital power meter, and determining a configuration associated with the input signal. The method also includes determining that a pulse width associated with the input signal is greater than a threshold, determining an offset associated with a special subframe configuration, and generating an estimated sync pulse. The method further includes forming a regenerated sync pulse, determining an error between the estimated sync pulse and the regenerated sync pulse, determining that the error is less than a threshold, and providing a lock detect.

Claims

1. A method of generating a synchronization switching pulse in a time division duplexing (TDD) system, the method comprising:

receiving an input signal at an input port of a digital power meter;

receiving, at the digital power meter, a power threshold level;

measuring, using the digital power meter, a power level associated with the input signal;

determining that the power level associated with the input signal exceeds the power threshold level;

determining, for the input signal, a number of rising edges, a number of falling edges, locations of the rising edges, and locations of the falling edges;

determining, for the input signal, one or more pulse widths measured between the locations of the rising edges and the falling edges;

determining a downlink/uplink configuration associated with the input signal;

determining that at least one of the one or more pulse widths is greater than a threshold;

forming an estimated sync pulse;

determining a special subframe configuration associated with the input signal;

determining an offset;

forming a regenerated sync pulse;

determining, using an error detector, an error between the estimated sync pulse and the regenerated sync pulse;

determining that the error is less than an error threshold; and

providing the regenerated sync pulse as the synchronization switching pulse.