CHIP PACKAGE AND POWER MODULE

• US 20200137879A1
• Filed: 10/25/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: LIU, Tsang-Yu, LEE, Po-Han, CHIEN, Wei-Ming
• Granted Patent: US 11,310,904 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08 of an individual bonding area
• CPC Class Codes: H01L 2224/08235 the bonding area connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/29139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73251 on different surfaces
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49872 the conductive materials containing semiconductor material
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0215 : Grounding of printed circuits by connection to external grounding means
• CPC Class Codes: H05K 1/0254 : High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection electrostatic discharge protection for electric apparatus in general H05K9/0067, H05K9/0079; Arrangements for regulating voltages or for using plural voltages
• CPC Class Codes: H05K 1/0346 : containing N
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2203/049 : Wire bonding

Abstract

A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.

Claims

1. A chip package, comprising:

a high voltage withstanding substrate having a main body, a functional layer and a grounding layer, the main body having a top surface and a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole, wherein the function layer is located on the top surface, and the grounding layer covers the bottom surface and the sidewall; and

a device chip located on the functional layer, and having a grounding pad that faces the main body, wherein the grounding pad is electrically connected to the grounding layer in the through hole.

2. The chip package of claim 1, wherein the functional layer is made of a material comprising gallium nitride (GaN).

3. The chip package of claim 1, wherein a thickness of the functional layer is in a range from 3 μ

m to 4 μ

m.

4. The chip package of claim 1, wherein the grounding layer substantially covers the entire bottom surface of the main body.

5. The chip package of claim 1, wherein a region of the grounding layer is greater than an area of the grounding pad.

6. The chip package of claim 1, wherein the grounding layer is made of a material comprising copper.

7. The chip package of claim 1, wherein the device chip has a bottom surface that faces the functional layer, and the grounding pad is located on the bottom surface of the device chip.

8. The chip package of claim 7, wherein the grounding pad is further located in the functional layer.

9. The chip package of claim 1, wherein the device chip has a bottom surface that faces the functional layer, and the grounding pad is located in the bottom surface of the device chip.

10. The chip package of claim 9, wherein the through hole and the grounding layer further extend into the functional layer.

11. The chip package of claim 10, wherein the through hole and the grounding layer further extend into the device chip.

12. The chip package of claim 1, wherein the device chip has a top surface facing away from the functional layer, and the top surface of the device chip has a conductive pad.

13. A power module, comprising:

a printed circuit board having a grounding region; and

a chip package located on the grounding region of the printed circuit board, comprising;

a high voltage withstanding substrate having a main body, a functional layer, and a grounding layer, the main body having a top surface and a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole, wherein the function layer is located on the top surface, the grounding layer covers the bottom surface and the sidewall, and the grounding layer is located on the grounding region of the printed circuit board and is electrically connected to the grounding region; and

a device chip located on the functional layer, and having a grounding pad facing the main body, wherein the grounding pad is electrically connected to the grounding layer in the through hole.

14. The power module of claim 13, wherein the printed circuit board has a wire bonding region, the device chip has a top surface facing away from the functional layer, the top surface of the device chip has a conductive pad, and the power module further comprises:

a conductive wire, wherein two ends of the conductive wire are respectively located on the wire bonding region and the conductive pad.

15. The power module of claim 13, further comprising:

a bonding conductive layer located between the grounding layer of the high voltage withstanding substrate and the grounding region of the printed circuit board.

16. The power module of claim 15, wherein the bonding conductive layer is silver paste or solder.