METHOD AND STRUCTURE FOR LAYOUT AND ROUTING OF PCB

• US 20200137880A1
• Filed: 06/13/2018
• Published: 04/30/2020
• Est. Priority Date: 09/26/2017
• Status: Active Grant

• Current Assignee: Zhengzhou Yunhai Information Technology Company Limited (Inspur Group Company Limited)
• Original Assignee: Zhengzhou Yunhai Information Technology Company Limited (Inspur Group Company Limited)
• Inventors: LI, Deheng
• Granted Patent: US 10,869,386 B2
• Time in Patent Office: Days
• CPC Class Codes: H05K 1/0218 by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 2201/09318 Core having one signal plane and one power plane
• CPC Class Codes: H05K 2201/09327 Special sequence of power, ground and signal layers in multilayer PCB
• CPC Class Codes: H05K 2201/09972 Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently

Abstract

Disclosed are a method and a structure for layout and routing of a PCB. The method includes: arranging signal lines, a power plane and a ground plane of the PCB in combination, where a portion of a reference plane for the signal lines is configured as a ground plane for providing a reference plane and return paths for the signal lines, to save routing spates. Layout of regions for the power supply, the ground and signal lines is appropriately designed, thereby improving the design density of a board, reducing the number of layers of the PCB, and saving cost.

Claims

1. A method for layout and routing of a PCB, comprising:

arranging signal lines, a power plane and a ground plane of the PCB in combination, wherein

a portion of a reference plane for the signal lines is configured as a ground plane for providing a reference plane and return paths for the signal lines.

2. The method for layout and routing of a PCB according to claim 1, comprising:

providing a PCB comprising 10 stacked layers, and

arranging a layout of signal lines and a power supply on each of the 10 stacked layers as;

3. The method for layout and routing of a PCB according to claim 2, wherein the layout of the PCB comprises:

a region for arranging PCH and PCIE slots, a region for arranging DIMM slots and CPU, and a region for QPI wiring, and the method comprises;

configuring a region of the L4 layer corresponding to the region for QPI wiring and the region for arranging DIMM slots and CPU for a ground plane, and configuring a remaining region of the L4 layer for a power plane; and

configuring a region of the L5 layer corresponds to the region for QPI wiring for arranging QPI signal lines, with the ground plane on the L4 layer being a reference plane corresponding to the QPI signal lines, and configuring a remaining region of the L5 layer for a power plane.

4. The method for layout and routing of a PCB according to claim 3, comprising:

configuring a region of the L6 layer corresponding to the region for QPI wiring for arranging QPI signal lines, configuring a region of the L6 layer corresponding to region for arranging PCH and PCIE slots for arranging high-speed lines and other lines, and configuring a region of the L6 layer corresponding to the region for arranging DIMM slots and CPU for a ground plane; and

configuring a region of the L7 layer corresponding to the region of the L6 layer configured for arranging QPI signal lines and the region of the L6 layer configured for arranging high-speed lines and other lines for a ground plane, for providing reference for the QPI signal lines and the high-speed lines on the L6 layer, and configuring a remaining region of the L7 layer for power supply.

5. A structure for layout and routing of a PCB, comprising:

signal lines, a power plane and a ground plane, wherein

a portion of a reference plane for signal lines is configured as a ground plane for providing a reference plane and return paths for the signal lines.

6. The structure for layout and routing of a PCB according to claim 5, wherein

the PCB comprising 10 stacked layers, and

a layout each of the 10 layers is:

7. The structure for layout and routing of a PCB according to claim 6, wherein the layout of the PCB comprises:

a region for arranging PCH and PCIE slots, a region for arranging DIMM slots and CPU, and a region for QPI wiring, wherein,

a region of the L4 layer corresponding to the region for QPI wiring and the region for arranging DIMM slots and CPU is configured for a ground plane, and a remaining region of the L4 layer is configured for a power plane; and

a region of the L5 layer corresponds to the region for QPI wiring is configured for arranging QPI signal lines, with the ground plane on the L4 layer being a reference plane corresponding to the QPI signal lines, and a remaining region of the L5 layer is configured for a power plane.

8. The structure for layout and routing of a PCB according to claim 7, wherein

a region of the L6 layer corresponding to the region for QPI wiring is configured for arranging QPI signal lines, a region of the L6 layer corresponding to region for arranging PCH and PCIE slots is configured for arranging high-speed lines and other lines, and a region of the L6 layer corresponding to the region for arranging DIMM slots and CPU is configured for a ground plane;

and

a region of the L7 layer corresponding to the region of the L6 layer configured for arranging QPI signal lines and the region of the L6 layer configured for arranging high-speed lines and other lines is configured for a ground plane, for providing reference for the QPI signal lines and the high-speed lines on the L6 layer, and a remaining region of the L7 layer is configured for power supply.