CONTROL CIRCUIT, SAMPLING CIRCUIT FOR SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY, METHOD OF READING PROCEDURE AND CALIBRATION THEREOF

• US 20200143868A1
• Filed: 11/01/2018
• Published: 05/07/2020
• Est. Priority Date: 11/01/2018
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: YU, Chun-Chi, Chou, Gerchih, Chang, Chih-Wei, Huang, Shen-Kuo
• Granted Patent: US 10,643,685 B1
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 Output synchronization

Abstract

The present disclosure provides a memory control circuit configured to precede a data-reading process with a memory. For the data-reading process, the memory transmits a DQ and a DQS indicating a time to read the DQ. The DQS includes a preamble. The memory control circuit includes a control circuit and a sampling circuit. The control circuit is configured to generate an enabling signal. The sampling circuit coupled to the control circuit is configured to sample the DQS based on the enabling signal in order to determine a sampling level. The control circuit determines whether the sampling level matches a signal level of the preamble or not.

Claims

1. A memory control circuit for processing a reading data procedure with a memory, wherein the memory transmits a DQ and a DQS indicating presenting time of the DQ in the reading data procedure, wherein the DQS comprises a preamble and a tristate portion followed by the preamble, wherein the memory control circuit comprises:

a clock generating circuit configured to generate a clock;

a control circuit coupled to the clock generating circuit, configured to generate an enabling signal based on the clock, and configured to transmit a control signal to the memory so as to make a signal level of the tristate portion maintain at a fixed level different from a signal level of the preamble; and

a sampling circuit coupled to the control circuit, and configured to sample the DQS to obtain a sampling level based on the enabling signal;

wherein the control circuit determines whether the sampling level matches a signal level of the preamble or not.

3. The memory control circuit of claim 1, wherein the control circuit comprises a coarse tuning clock edge selector, the coarse tuning clock edge selector is configured to output a coarse tune clock, wherein when the sampling level matches the fixed level, the sampling circuit samples the DQS based on the coarse tune clock outputted by the coarse tuning clock edge selector, and determines whether a signal position, which is currently sampled, is in the tristate portion or not.

4. The memory control circuit of claim 3, wherein the control circuit comprise a fine tuning delay controller, the fine tuning delay controller is configured to generate a delay time, the delay time is less than the clock, wherein when the sampling level does not match the fixed level, the control circuit sets the signal position currently sampled as a switch point, wherein the switch point is in the preamble.

5. The memory control circuit of claim 4, wherein the control circuit determines whether a signal level sampled at a position, which is generated by adding a shift value to the switch point, matches the signal level of the preamble, wherein the shift value comprises 0 clock cycle, 0.5 clock cycle, and 1 clock cycle.

6. The memory control circuit of claim 5, wherein if the control circuit determines the signal level sampled at the position, which is generated by adding the shift value to the switch point, matches the signal level of the preamble, the control circuit determines whether the signal level that sampled at the position, which is generated by adding the shift value and the delay time to the switch point, matches the signal level of the preamble or not.

7. The memory control circuit of claim 5, wherein if the control circuit determines the signal level sampled at the position, which is generated by adding the shift value and the delay time to the switch point, matches the signal level of the preamble, the control circuit controls the sampling circuit to sample the DQS based on the delay time.

8. The memory control circuit of claim 6, wherein if the control circuit determines the signal level sampled at the position, which is generated by adding the shift value and the delay time to the switch point, does not match the signal level of the preamble, the control circuit calculates a signal position, which is generated by adding a total delay time to the switch point, and sets the signal position as a calibration position of the preamble, wherein the signal level of the preamble is high level signal or low level signal.

9. The memory control circuit of claim 6, wherein the preamble is one clock cycle, wherein half of the clock cycle is in high level and another half of the clock cycle is in low level, and when the control circuit determines that the sampled signal does not match the signal level of the preamble, the control circuit calculates a signal position, which is generated by adding a total delay time to and subtracting a quarter of clock cycle to the switch point, and sets the signal position as a calibration position of the preamble.

10. The memory control circuit of claim 6, wherein the preamble is two clock cycles, wherein one and a half of the clock cycle is in high level and half of the clock cycle is in low level, and when the control circuit determines that the sampled signal does not match the signal level of the preamble, the control circuit calculates the signal position, which is generated by adding a total delay time to and subtracting a quarter of clock cycle to the switch point, and sets the signal position as a calibration position of the preamble.

2. (canceled)

11. A calibrating method configured to a reading data procedure between a memory control circuit and a memory, the memory control circuit comprises a clock generating circuit, a control circuit and a sampling circuit, wherein the memory transmits a DQ and a DQS indicating presenting time of the DQ in the reading data procedure, wherein the DQS comprises a preamble and a tristate portion followed by the preamble, wherein the method comprises:

generating a clock by the clock generating circuit;

generating an enabling signal by the control circuit;

transmitting a control signal to the memory by the control circuit so as to make a signal level of the tristate portion maintain at a fixed level different from a signal level of the preamble;

sampling the DQS based on the enabling signal by the sampling circuit to obtain a sampling level; and

determining whether the sampling level matches a signal level of the preamble or not by the control circuit.

13. The calibrating method of claim 11, further comprising:

outputting a coarse tune clock by a coarse tuning clock edge selector of the control circuit; and

when the sampling level matches the fixed level, the sampling circuit samples the DQS based on the coarse tune clock outputted by the coarse tuning clock edge selector, in order to determine whether a signal position, which is currently sampled, is in the tristate portion or not.

14. The calibrating method of claim 13, further comprising:

generating a delay time by a fine tuning delay controller of the control circuit, and the delay time is less than the clock; and

when the sampling level does not match the fixed level, the control circuit sets the signal position currently sampled as a switch point, wherein the switch point is in the preamble.

15. The calibrating method of claim 14, further comprising:

determining whether a signal level sampled at a position, which is generated by adding a shift value to the switch point, matches the signal level of the preamble, wherein the shift value comprises 0 clock cycle, 0.5 clock cycle and 1 clock cycle.

16. The calibrating method of claim 15, further comprising:

if determining the signal level sampled at the position, which is generated by adding the shift value to the switch point, matches the signal level of the preamble, determining whether the signal level that sampled at the position, which is generated by adding the shift value and the delay time to the switch point, matches the signal level of the preamble or not.

17. The calibrating method of claim 15, further comprising:

if determining the signal level sampled at the position, which is generated by adding the shift value and the delay time to the switch point, matches the signal level of the preamble, controlling the sampling circuit to sample the DQS based on the delay time.

18. The calibrating method of claim 16, further comprising:

if determining the signal level sampled at the position, which is generated by adding the shift value and the delay time to the switch point, does not match the signal level of the preamble, calculating a signal position, which is generated by adding a total delay time to the switch point, and setting the signal position as a calibration position of the preamble, wherein the signal level of the preamble is high level signal or low level signal.

19. The calibrating method of claim 16, further comprising:

when the preamble is one clock cycle, and when the control circuit determines that the sampled signal does not match the signal level of the preamble, the control circuit calculates a signal position, which is generated by adding a total delay time to and subtracting a quarter of clock cycle to the switch point, and sets the signal position as a calibration position of the preamble, wherein half of the clock cycle is in high level and half of the clock cycle is in low level.

20. The calibrating method of claim 16, further comprising:

when the preamble is two clock cycles, and when the control circuit determines that the sampled signal does not match the signal level of the preamble, the control circuit calculates the signal position, which is generated by adding a total delay time to and subtracting a quarter of clock cycle to the switch point, and sets the signal position as a calibration position of the preamble, wherein one and a half of the clock cycle is in high level clock cycle and half of the clock cycle is in low level clock cycle.

12. (canceled)