Time compression storage circuit
First Claim
6. A TIME COMPRESSION STORAGE CIRCUIT TO WHICH IS APPLIED AN ELECTRICAL SIGNAL TO BE STORED, COMPRISING GATING MEANS FOR SAMPLING SAID SIGNAL AT A FIXED TIME INTERVAL TO OBTAIN SAMPLED INFORMATION IN THE FORM OF INFORMATION BITS, A FIRST PATH CLOSED THROUGH A SERIES CONNECTION OF A SILICA DELAY LINE AND A POST DELAY AMPLIFIER, SAID PATH INCLUDING A DELAY CABLE, AN INHIBIT CIRCUIT AND A FIRST LINE DRIVER AMPLIFIER COUPLED TOGETHER IN THE ORDER RECITED, THE INPUT TO SAID DELAY CABLE BEING COUPLED TO THE OUTPUT OF SAID POST DELAY AMPLIFIER AND THE OUTPUT OF SAID FIRST LINE DRIVER AMPLIFIER BEING CONNECTED TO THE INPUT OF SAID DELAY LINE, MEANS FOR INTRODUCING SAID INFORMATION BITS INTO SAID FIRST PATH, A SECOND PATH ALSO CLOSED THROUGH SAID SILICA DELAY LINE AND SAID POST DELAY AMPLIFIER TO WHICH IS INTRODUCED A SYNCHRONIZING PULSE FOR ACTUATING SAID GATING MEANS, THE AMPLITUDE OF SAID SYNCHRONIZING PULSE BEING SEVERAL MAGNITUDES GREATER THAN THE AMPLITUDE OF SAID INFORMATION BITS, SAID SECOND PATH INCLUDING A THRESHOLD DETECTOR, A SYNCHRONIZING PULSE REGENERATOR AND A SECOND LINE DRIVER AMPLIFIER COUPLED TOGETHER IN THE ORDER RECITED, THE INPUT TO SAID THRESHOLD DETECTOR BEING CONNECTED IN COMMON WITH THE INPUT OF SAID DELAY CABLE TO THE OUTPUT OF SAID POST DELAY AMPLIFIER AND THE OUTPUT OF SAID SECOND LINE DRIVER AMPLIFIER BEING CONNECTED IN COMMON WITH THE OUTPUT OF SAID FIRST LINE DRIVER AMPLIFIER TO THE INPUT OF SAID DELAY LINE, SAID INHIBIT CIRCUIT ACTING TO PASS SAID INFORMATION BITS INTO SAID FIRST PATH AND TO BLOCK SAID SYNCHRONIZING PULSE, AND SAID THRESHOLD DETECTOR ACTING TO PASS SAID SYNCHRONIZING PULSE INTO SAID SECOND PATH WHILE REJECTING SAID INFORMATION BITS, SAID DELAY CABLE HAVING A DELAY OF TWO BIT TIME INTERVALS AND SAID SYNCHRONIZING PULSE REGENERATOR PROVIDING A DELAY OF THREE BIT TIME INTERVALS, WHEREBY SAID INFORMATION BITS ARE RECIRCULATED THROUGH SAID FIRST CLOSED PATH ONCE PER FIXED TIME INTERVAL AND ARE STORED IN SAID DELAY LINE IN ADJACENT BIT TIME INTERVALS WITH THE SYNCHRONIZING PULSE FOLLOWING SAID INFORMATION BITS AND SEPARATED BY ONE BLANK INTERVAL FROM THE MOST RECENT INFORMATION BIT, SAID INFORMATION BITS FORMING A TIME COMPRESSED SIGNAL CORRESPONDING TO THE APPLIED SIGNAL WHICH IS COMPRESSED IN TIME BY AN AMOUNT EQUAL TO THE RATIO OF SAID FIXED TIME INTERVAL TO SAID BIT TIME INTERVAL.
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6 Claims
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6. A TIME COMPRESSION STORAGE CIRCUIT TO WHICH IS APPLIED AN ELECTRICAL SIGNAL TO BE STORED, COMPRISING GATING MEANS FOR SAMPLING SAID SIGNAL AT A FIXED TIME INTERVAL TO OBTAIN SAMPLED INFORMATION IN THE FORM OF INFORMATION BITS, A FIRST PATH CLOSED THROUGH A SERIES CONNECTION OF A SILICA DELAY LINE AND A POST DELAY AMPLIFIER, SAID PATH INCLUDING A DELAY CABLE, AN INHIBIT CIRCUIT AND A FIRST LINE DRIVER AMPLIFIER COUPLED TOGETHER IN THE ORDER RECITED, THE INPUT TO SAID DELAY CABLE BEING COUPLED TO THE OUTPUT OF SAID POST DELAY AMPLIFIER AND THE OUTPUT OF SAID FIRST LINE DRIVER AMPLIFIER BEING CONNECTED TO THE INPUT OF SAID DELAY LINE, MEANS FOR INTRODUCING SAID INFORMATION BITS INTO SAID FIRST PATH, A SECOND PATH ALSO CLOSED THROUGH SAID SILICA DELAY LINE AND SAID POST DELAY AMPLIFIER TO WHICH IS INTRODUCED A SYNCHRONIZING PULSE FOR ACTUATING SAID GATING MEANS, THE AMPLITUDE OF SAID SYNCHRONIZING PULSE BEING SEVERAL MAGNITUDES GREATER THAN THE AMPLITUDE OF SAID INFORMATION BITS, SAID SECOND PATH INCLUDING A THRESHOLD DETECTOR, A SYNCHRONIZING PULSE REGENERATOR AND A SECOND LINE DRIVER AMPLIFIER COUPLED TOGETHER IN THE ORDER RECITED, THE INPUT TO SAID THRESHOLD DETECTOR BEING CONNECTED IN COMMON WITH THE INPUT OF SAID DELAY CABLE TO THE OUTPUT OF SAID POST DELAY AMPLIFIER AND THE OUTPUT OF SAID SECOND LINE DRIVER AMPLIFIER BEING CONNECTED IN COMMON WITH THE OUTPUT OF SAID FIRST LINE DRIVER AMPLIFIER TO THE INPUT OF SAID DELAY LINE, SAID INHIBIT CIRCUIT ACTING TO PASS SAID INFORMATION BITS INTO SAID FIRST PATH AND TO BLOCK SAID SYNCHRONIZING PULSE, AND SAID THRESHOLD DETECTOR ACTING TO PASS SAID SYNCHRONIZING PULSE INTO SAID SECOND PATH WHILE REJECTING SAID INFORMATION BITS, SAID DELAY CABLE HAVING A DELAY OF TWO BIT TIME INTERVALS AND SAID SYNCHRONIZING PULSE REGENERATOR PROVIDING A DELAY OF THREE BIT TIME INTERVALS, WHEREBY SAID INFORMATION BITS ARE RECIRCULATED THROUGH SAID FIRST CLOSED PATH ONCE PER FIXED TIME INTERVAL AND ARE STORED IN SAID DELAY LINE IN ADJACENT BIT TIME INTERVALS WITH THE SYNCHRONIZING PULSE FOLLOWING SAID INFORMATION BITS AND SEPARATED BY ONE BLANK INTERVAL FROM THE MOST RECENT INFORMATION BIT, SAID INFORMATION BITS FORMING A TIME COMPRESSED SIGNAL CORRESPONDING TO THE APPLIED SIGNAL WHICH IS COMPRESSED IN TIME BY AN AMOUNT EQUAL TO THE RATIO OF SAID FIXED TIME INTERVAL TO SAID BIT TIME INTERVAL.
Specification
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Current AssigneeJoseph P. Hesler, William Peil
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Original AssigneeJoseph P. Hesler, William Peil
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InventorsHesler, Joseph P., Peil, William
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Application NumberUS04/079,424Time in Patent Office1,321 DaysField of SearchUS Class Current365/77CPC Class CodesG11C 21/00 Digital stores in which the...
