Electronic data processor

• US 3,161,856 A
• Filed: 12/09/1960
• Issued: 12/15/1964
• Est. Priority Date: 12/09/1960
• Status: Expired due to Term

• Current Assignee: Charles H. Jr. Propster, Joyce L. Barbe
• Original Assignee: Charles H. Jr. Propster, Joyce L. Barbe
• Inventors: Propster, Charles H. Jr., Barbe, Joyce L.
• Application Number:
  US04/074,976
• Time in Patent Office: 1,467 Days
• US Class Current: 712/234
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 9/30058 Conditional branch instructions

Claims

1. IN A SERIAL, STORED-PROGRAM, DIGITAL COMPUTER HAVING AN INSTRUCTION SEQUENCING SECTION FOR CONTROLLING THE EXECUTION OF SINGLE-ADDRESS AND ONE-PLUS-ONE ADDRESS INSTRUCTIONS, SAID ONE-PLUS-ONE ADDRESS INSTRUCTION CONSISTING OF TWO GROUPS OF DIGITAL SIGNALS, A FIRST GROUP OF A GIVEN ONE-PLUS-ONE ADDRESS INSTRUCTION SPECIFYING AN OPERATION TO COMPARE THE ABSOLUTE VALUE OF A GIVEN NUMBER WITH THE ABSOLUTE VALUE OF A SPECIFIED CONSTANT AND TO BRANCH TO AN ALTERNATIVE SEQUENCE OF INSTRUCTIONS BEGINNING WITH AN INSTRUCTION AT AN ADDRESS SPECIFIED BY A SECOND GROUP OF DIGITAL SIGNALS IF A SPECIFIED RELATION IS PRESENT BETWEEN THE VALUE OF SAID GIVEN NUMBER AND THE VALUE OF SAID SPECIFIED CONSTANT, SAID SPECIFIED CONSTANT BEING REPRESENTED BY A PORTION OF SAAID FIRST GROUP OF DIGITAL SIGNALS WHICH GROUP INCLUDES TWO DISTINCTIVE DIGITAL SIGNALS, THE COMBINATION COMPRISING:

A MEMORY SECTION HAVING A PLURALITY OF SEQUENTIALLY ACCESSIBLE MEMORY LOCATIONS;

A FIRST AND SECOND REGISTER;

A THIRD REGISTER FOR STORING A GROUP OF DIGITAL SIGNALS REPRESENTING SAID GIVEN NUMBER;

FIRST MEANS FOR TRANSFERRING SAID FIRST GROUP OF DIGITAL SIGNALS TO SAID FIRST REGISTER INCLUDING A SERIAL BINARY ADDER THROUGH WHICH SAID FIRST GROUP OF DIGITAL SIGNALS IS SERIALLY TRANSFERRED TO SAID FIRST REGISTER;

SENSING MEANS FOR DETERMINING THE PRESENCE OF SAID TWO DISTINCTIVE DIGITAL SIGNALS OF SAID FIRST GROUP OF DIGITAL SIGNALS;