Alternating current diode loop capacitance measurement circuits

• US 3,271,669 A
• Filed: 12/04/1962
• Issued: 09/06/1966
• Est. Priority Date: 12/04/1962
• Status: Expired due to Term

• Current Assignee: Tenny Lode
• Original Assignee: Tenny Lode
• Inventors: TENNY LODE
• Application Number:
  US04/242,166
• Time in Patent Office: 1,372 Days
• US Class Current: 324/679
• CPC Class Codes: G01L 13/025 using diaphragms
• CPC Class Codes: G01L 9/0072 using variations in capacitance
• CPC Class Codes: G01L 9/12 by making use of variations in capacitance , i.e. electric circuits therefor
• CPC Class Codes: G01R 27/02 Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant by measuring phase angle only G01R25/00
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24

Claims

1. CAPACITOR COMPARATOR CIRCUITRY COMPRISING FIRST NETWORK INCLUDING FIRST AND SECOND CAPACITORS WHICH ARE VARIABLE RELATIVE TO EACH OTHER, SAID FIRST CAPACITOR BEING CONNECTED FOR CONDUCTION BETWEEN A FIRST INPUT TERMINAL AND A FIRST JUNCTION AND SAID SECOND CAPACITOR BEING CONNECTED FOR CONDUCTION BETWEEN SAID FIRST INPUT TERMINAL AND A THIRD JUNCTION, FIRST, SECOND THIRD AND FOURTH DIODES ALL CONNECTED FOR CONDUCTION IN THE SAME DIRECTION IN A CLOSED SERIES LOOP WITH A SECOND INPUT TERMINAL ON SAID LOOP BETWEEN THE FIRST AND SECOND DIODES, SAID FIRST JUNCTION BEING ON SAID LOOP BETWEEN THE SECOND AND THIRD DIODES, A SECOND JUNCTION ON SAID LOOP BETWEEN THE THIRD AND FORUTH DIODES AND SAID THIRD JUNCTION BEING ON SAID LOOP BETWEEN THE FOURTH AND FIRST DIODES, A BASE LOAD CONNECTED BETWEEN SAID SECOND INPUT TERMINAL AND SECOND JUNCTION, ALTERNATING VOLTAGE SUPPLY MEANS HAVING OUTPUT AND BASE POTENTIAL TERMINALS FOR SUPPLYING POWER TO SAID FIRST AND SECOND INPUT TERMINALS COMPRISING AN OSCILLATOR HAVING A SIGNAL INPUT, OUTPUT AND BASE POTENTIAL TERMINALS, SAID OUTPUT BEING AMPLITUDE-CONTROLLED BY A UNIDIRECTIONAL VOLTAGE INPUT SIGNAL, AN AMPLIFIER HAVING AN INPUT SUMMING POINT AND AN UNIDIRECTIONAL VOLTAGE OUTPUT COUPLED TO THE OSCILLATOR SIGNAL INPUT FOR SUPPLYING SIGNAL INPUT THERETO, AT LEAST ONE NETWORK ENERGIZED BY THE OSCILLATOR OUTPUT, SAID NETWORK COMPRISING A CAPACITOR, HAVING FIRST AND SECOND TERMINALS, SAID FIRST TERMINAL BEING ENERGIZED BY THE OSCILLATOR OUTPUT, SAID CAPACITOR BEING OF A SIZE SUCH THAT IT IS SUBSTANTIALLY FULLY RECHARGED BY EACH CYCLE OF ALTERNATING CURRENT IMPOSED THEREON, CURRENT CARRYING MEANS COUPLED TO SAID CAPACITOR SECOND TERMINAL FOR CONDUCTION OF CAPACITOR CHARGE AND DISCHARGE CYCLES TO SAID BASE POTENTIAL AND SUMMING POINT, RESPECTIVELY, AND A UNIDIRECTIONAL VOLTAGE REFERENCE CONNECTED FOR CONDUCTION TO SAID SUMMING POINT, WHEREBY SAID ALTERNATING VOLTAGE SUPPLY MEANS OUTPUT AMPLITUDE IS CONTROLLED BY A SUMMATION OF CURRENTS FROM SAID REFERENCE AND NETWORK CURRENTS.