Process for fabricating electrical circuits

• US 3,337,426 A
• Filed: 06/04/1964
• Issued: 08/22/1967
• Est. Priority Date: 06/04/1964
• Status: Expired due to Term

• Current Assignee: John E. Celto
• Original Assignee: John E. Celto
• Inventors: Celto, John E.
• Application Number:
  US04/372,468
• Time in Patent Office: 1,174 Days
• US Class Current: 205/125
• CPC Class Codes: C23C 14/04 Coating on selected surface areas, e.g. using masks
• CPC Class Codes: H10N 97/00 Electric solid-state thin-film or thick-film devices, not otherwise provided for

Claims

1. A METHOD OF ELECTRICAL CIRCUIT FABRICATION WHICH COMPRISES THE STEPS OF DEPOSITING A FIRST CONDUCTIVE LAYER ON AN INSULATION SUBSTRATE, CONVERTING THE SURFACE OF SAID FIRST CONDUCTIVE LAYER TO A NONCONDUCTING DIELECTRIC, APPLYING A FIRST RESIST PATTERN DEFINING CAPACITOR BASE ELECTRODES TO SAID NONCONDUCTING DIELECTRIC, CONVERTING THE RMAINDER OF SAID CONDUCTIVE LAYER EXPOSED BY SAID FIRST RESIST PATTERN TO A NON-CONDUCTING DIELECTRIC, REMOVING SAID FIRST RESIST PATTERN, DEPOSITING A LAYER OF ELECTRICAL RESISTOR MATERIAL ON THE SURFACE OF SAID NONCONDUCTING DIELECTRIC, DEPOSITING A SECOND CONDUCTIVE LAYER ON SAID LAYER OF ELECTRICAL RESISTOR MATERIAL, APPLYING A SECOND RESIST PATTERN DEFINING RESISTORS AND CONDUCTORS TO SAID SECOND CONDUCTIVE LAYER, REMOVING SAID LAYER OF ELECTRICAL RESISTOR MATERIAL AND SAID SECOND CONDUCTIVE LAYER WHERE EXPOSED BY SAID SECOND RESIST PATTERN, REMOVING SAID SECOND RESIST PATTERN, APPLYING A THIRD RESIST PATTERN DEFINING CONDUCTORS TO THE REMAINDER OF SAID ELECTRICAL RESISTOR LAYER, AND REMOVING SAID CONDUCTIVE LAYER EXPOSED BY SAID THIRD RESIST PATTER.