SAMPLE AND HOLD CIRCUIT

• US 3,430,072 A
• Filed: 01/11/1966
• Issued: 02/25/1969
• Est. Priority Date: 01/11/1966
• Status: Expired due to Term

• Current Assignee: Daniel A. Stevens
• Original Assignee: Daniel A. Stevens
• Inventors: Stevens, Daniel A.
• Application Number:
  US04/520,312
• Time in Patent Office: 1,141 Days
• US Class Current: 327/95
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H03K 17/06 Modifications for ensuring a fully conducting state

Claims

1. AN ELECTRONIC SAMPLE AND HOLD CIRCUIT WHICH SAMPLES A VOLTAGE WAVEFORM FOR A SHORT PERIOD OF TIME AND STORES A PROPORTIONAL DIRECT CURRENT (DC) VOLTAGE FOR A MUCH LONGER TIME, COMPRISING:

SERIES RESISTOR HAVING ONE LEAD ADAPTED TO BE COUPLED TO A VOLTAGE WAVEFORM SOURCE;

A WIDEBAND DC AMPLIFYING MEANS HAVING INPUT AND OUTPUT MEANS, SAID INPUT MEANS COUPLED TO THE OTHER LEAD OF SAID SERIES RESISTOR;

A GATING MEANS, WHICH FUNCTIONS AS AN ELECTRONIC SWITCH HAVING THREE TERMINALS, THE FIRST SAID TERMINAL IS AN INPUT TERMINAL WHICH RECEIVES GATING PULSES AND CONTROLS SAID ELECTRONIC SWITCH TO ITS OPEN AND CLOSED CONDITIONS, AND THE SECOND SAID TERMINAL IS COUPLED TO SAID OUTPUT MEANS OF SAID DC AMPLIFYING MEANS;

A STORAGE CIRCUIT MEANS, HAVING A CAPACITOR, A LOAD RESISTOR, AND A FIELD EFFECT TRANSISTOR HAVING A SOURCE ELECTRODE, A DRAIN ELECTRODE, AND A GATE ELECTRODE, SAID GATE ELECTRODE BEING COUPLED TO ONE LEAD OF SAID CAPACITOR AND TO THE THIRD OF SAID THREE GATING MEANS TERMINALS, THE OPPOSITE LEAD OF SAID CAPACITOR BEING COUPLED TO A POINT OF GROUND POTENTIAL, SAID DRAIN ELECTRODE BEING COUPLED TO A FIRST VOLTAGE SOURCE, SAID SOURCE ELECTRODE BEING COUPLED TO ONE LEAD OF SAID LOAD RESISTOR AND CONSTITUTING AN OUTPUT OF SAID SAMPLE AND HOLD CIRCUIT, AND THE OPPOSITE LEAD OF SAID LOAD RESISTOR BEING COUPLED TO A SECOND VOLTAGE SOURCE OF OPPOSITE POLARITY TO SAID FIRST VOLTAGE SOURCE;

AND