HIGH NOISE IMMUNITY SYSTEM FOR INTEGRATED CIRCUITS

• US 3,553,486 A
• Filed: 03/06/1968
• Issued: 01/05/1971
• Est. Priority Date: 03/06/1968
• Status: Expired due to Term

• Current Assignee: Bruce R. Dow
• Original Assignee: Bruce R. Dow
• Inventors: Dow, Bruce R.
• Application Number:
  US04/710,853
• Time in Patent Office: 1,035 Days
• US Class Current: 326/22
• CPC Class Codes: H03K 19/084 Diode-transistor logic

Abstract

An input logic circuit for integrated circuits, particularly integrated circuits utilized in digital or pulse systems, prevents spurious signals (i.e., noise) from causing false triggering of the integrated circuit components.

Claims

1. For use with electrical apparatus adapted to be actuated by electrical pulses applied to an input terminal;

the combination of circuitry for preventing signals other than those having a predetermined amplitude from actuating said electrical apparatus, comprising a pair of terminals adapted for connection to a source of driving potential, a pair of transistors each having base, emitter and collector electrodes, means interconnecting the base electrodes of said transistors, means electrically connecting one of the two remaining electrodes of each transistor to one of said driving potential terminals, means including an impedance element connecting said interconnected bases to the other driving potential terminal, means short circuiting the base and the other of the two remaining electrodes of one of said transistors, a pair of impedance elements connecting the other of the two remaining electrodes of the other transistor to said other driving potential terminal, at least one diode for connecting said input terminal to the junction of said last-mentioned impedance elements, and means for connecting said other of the two remaining electrodes of said other transistor to the input of said electrical apparatus.

2. The combination of claim 1 wherein said one of the two remaining electrodes of each transistor comprises the emitter of each transistor and the other of the two remaining electrodes of each transistor comprises its collector electrode.

3. The combination of claim 1 wherein said impedance elements comprise resistors.

4. The combination of cLaim 1 wherein said transistors comprise NPN transistors, said input terminal is connected to the cathode of said diode, and the anode of said diode is connected to the junction of said last-mentioned impedance elements.

5. The combination of claim 1 including a capacitor connecting one of said two last-mentioned impedance elements to one of said driving potential terminals.

6. The combination of claim 1 wherein at least said transistors and said diode are formed on a single silicon wafer.

7. The combination of claim 1 including a plurality of diodes each having its anode connected to the junction of said last-mentioned impedance elements.

8. The combination of claim 1 wherein the means connecting said interconnected bases to the other driving potential terminal includes a first resistor having one end connected to said interconnected bases and its other end connected to a movable tap on a variable resistor, said variable resistor being one of said last-mentioned impedance elements.