APPARATUS AND TECHNIQUES FOR GENERATING VARIABLE DELAY PULSES FROM PARALLELED AVALANCHE TRANSISTORS

• US 3,555,301 A
• Filed: 11/09/1967
• Issued: 01/12/1971
• Est. Priority Date: 11/09/1967
• Status: Expired due to Term

• Current Assignee: James P. Hansen
• Original Assignee: James P. Hansen
• Inventors: Hansen, James P.
• Application Number:
  US04/681,678
• Time in Patent Office: 1,160 Days
• US Class Current: 327/264
• CPC Class Codes: H03K 3/335 by the use, as active elements, of semiconductor devices with more than two electrodes and exhibiting avalanche effect
• CPC Class Codes: H03K 5/15086 using a plurality of monostables devices

Abstract

Apparatus for generating variable delay pulses from paralleled avalanche transistors wherein the individual transistor collector bias voltages can be adjusted so as to control the time at which each of the transistors avalanche when a triggering signal is applied to each of the transistors. The invention described herein may be manufactured and used by or for the Government of the United States of America for Governmental purposes without the payment of any royalties thereon or therefor.

Claims

1. A pulse generator, comprising:

means for storing an electrical charge;

means coupled to said charge storing means for selectively varying the charge thereon, wherein said charge varying means includes a DC voltage source, an adjustable voltage divider coupled between said voltage source and said charge storing means, and a transformer having a secondary winding coupled to said transistor and to said voltage divider and having a primary winding in operative relationship with said secondary winding;

a plurality of avalanche transistors, said transistors having their emitters in common and driving a common load, said transistors coupled to said charge storing means, said transistors being biased by said storing means such that they do not trigger for a predetermined period of time; and

input means coupled to said transistor for enabling the transmission of a trigger signal to said transistors;

said transformer modulating said transistors output signal.

2. A variable delay pulse generator, comprising:

a plurality of avalanche transistors having the emitters thereof in electrical common and driving a common load;

means coupled to each of said transistors for storing an electrical charge;

means coupled to each of said storing means for selectively varying the charges therein; and

input means electrically coupled together and coupled to each of said transistors for enabling the transmission of a trigger signal to each of said transistors.

3. A variable delay pulse generator, comprising:

a plurality of avalanche transistors having the emitter thereof in electrical common;

means coupled to each of said transistors for storing an electrical charge;

means coupled to each of said storing means for selectively varying the charges therein, wherein each of said charge varying means includes, a DC voltage source, an adjustable voltage divider coupled between said voltage source and a respective one of said charge storing means whereby each of said transistors may trigger at different input voltages, and a laser diode coupled to the emitters of said transistors; and

input means electrically coupled together and coupled to each of said transistors for enabling the transmission of a trigger signal to each of said transistors.

4. The pulse generator of claim 3 wherein eaCh of said charge-storing means includes a capacitor coupled to the collector of each of said avalanche transistors.

5. The pulse generator of claim 3 wherein each of said input means includes:

biasing and impedance matching resistors coupled to the base of each of said transistors.

6. The pulse generator of claim 3 wherein each of said charge-varying means includes:

a DC voltage source;

an adjustable voltage divider coupled between said voltage source and a respective one of said charge-storing means; and

a transformer having a secondary winding coupled to a respective transistor and to said voltage divider and having a primary winding in operative relationship with said secondary winding. a transformer having a secondary winding coupled to a respective transistor and to said voltage divider and having a primary winding in operative relationship with said secondary winding.