PSEUDO-RANDOM 4-LEVEL M-SEQUENCES GENERATORS

• US 3,557,356 A
• Filed: 05/06/1968
• Issued: 01/19/1971
• Est. Priority Date: 05/12/1967
• Status: Expired due to Term

• Current Assignee: Claude Balza, Maniere Maurice Auguste Franco
• Original Assignee: Claude Balza, Maniere Maurice Auguste Franco
• Inventors: Balza, Claude, MANIERE MAURICE AUGUSTE FRANCO
• Application Number:
  US04/726,686
• Time in Patent Office: 988 Days
• US Class Current: 708/256
• CPC Class Codes: G06F 7/584 using finite field arithmetic, e.g. using a linear feedback shift register

Abstract

Electronic apparatus for generating pseudo-random sequences of 4-level signals, comprising combinations of electronic devices capable of simulating the two possible operations on a 4-element Galois'"'"''"'"' field. The combinations include various logic circuits of the '"'"''"'"''"'"''"'"'AND, EXCLUSIVE OR'"'"''"'"''"'"''"'"' and '"'"''"'"''"'"''"'"'INVERTER'"'"''"'"''"'"''"'"' types.

Claims

1. Pseudorandom multilevel signal generating apparatus having a first and a second utilization terminal and comprising a number m of apparatus stages having respective ranks (j+1), where j varies from zero to (m-1), in which:

each of said apparatus stages having a rank Differing from 1 has a first, a second, a third and a fourth input and a first, a second, a third and a fourth output;

the apparatus stage of rank 1 has a first and a second input and a first, a second, a third and a fourth output and a said stage of rank 1 is provided with direct connections connecting its first and second outputs with said first and second utilization terminals;

each of said apparatus stages having a given rank other than 1 is provided with direct connections respectively connecting its first and second outputs and its third and fourth inputs with the first and second inputs and the third and fourth outputs of the apparatus stage of immediately lower rank than said given rank;

the apparatus stage of rank m is also provided with direct connections respectively connecting its first and second inputs with its third and fourth outputs;

each of said apparatus stages having any rank (j+1) comprises the two stages having same said rank (j+1) of a first and a second shift registers each having m register stages and both of which are driven from a common shift pulse source, while the inputs of said register stages of rank (j+1) in said first and second registers respectively constitute the above said first and second inputs of said apparatus stage of same rank (j +1), and while the outputs of same said register stages of rank (j+1) in said first and second registers respectively constitute the above said first and second outputs of said apparatus stage of rank (j +1);

said apparatus further comprising in each one of rank (j +1) of said apparatus stages an electronic multiplication and addition means having a first and a second input respectively fed from said first and second outputs of same said stage of rank (j +1) and having a first and a second output respectively constituting said third and fourth outputs of same said stage of rank (j +1) and further having except in stage of rank 1 a third and a fourth input respectively constituting said third and fourth inputs of same said stage of rank (j +1);

said electronic means effecting the multiplication in a four-element field constituted by the four existing pairs of electric signals each comprising a first and a second signal having either of two possible values, said field corresponding element by element to a standard Galois'"'"''"'"' field with elements designated as 0, 1, a, b, the first two of which being of which being respectively additive and multiplicative identity elements, and a conventional correspondence between respective elements of said field and said standard Galois'"'"''"'"' field being previously chosen, said multiplication in said Galois'"'"''"'"' field applying to an undetermined one of said four signal pairs, designated as ai+j, and to a selected coefficient hj equal to a predetermined one among said elements 0, 1, a, b, said first and second signal of said pair ai+j respectively appearing at said first and second outputs of said apparatus stage of rank (j+1) and being applied at said first and second input of said electronic means, and said electronic means thereafter effecting the addition in same said Galois'"'"''"'"' field of the pair of signals resulting of said multiplication to a pair of a first and a second signal respectively applied to said third and fourth inputs of same said stage of rank (j+1) and delivering a new signal pair resulting from said addition in same said Galois'"'"''"'"' field, said first and second signals of said new signal pair appearing respectively at said third and fourth outputs of latter said stage; and

whereby there is obtained at said third and fourth output of said apparatus stage of rank m a new signal pair ai+m defined by the recurrent relationship in said Galois'"'"''"'"' field;

2. Apparatus as claimed in claim 1 having its stage of rank 1 for which said selected coefficient is equal to said element b and in which said electronic means includes one '"'"''"'"''"'"''"'"'EXCLUSIVE OR'"'"''"'"''"'"''"'"' logic circuit having a first and a second input and one output, a direct connection between said first input of said electronic means and first input of said logic circuit, direct connections between said second input of said electronic means and respectively first output of said electronic means and second input of said logic circuit and a direct connection between said output of said logic circuit and said second output of said electronic means.

3. Apparatus as claimed in claim 1 having its stage of rank 1 for which said selected coefficient is equal to said element 1 and in which said electronic means includes a direct connection between its first input and first output and a direct connection between its second input and second output.

4. Apparatus as claimed in claim 1 having its stage of rank 1 for which said selected coefficient is equal to said element a and in which said electronic means includes one '"'"''"'"''"'"''"'"'EXCLUSIVE OR'"'"''"'"''"'"''"'"' logic circuit having a first and a second input and one output, direct connections between said first input of said electronic means and respectively first input of said logic circuit and second output of said electronic means, a direct connection between second input of said electronic means and second input of said logic circuit and a direct connection between said output of said logic circuit and said first output of said electronic means.

5. Apparatus as claimed in claim 1, for which said previously chosen conventional correspondence is characterized as follows, letters Z and U designating above said two possible values of said first and second signals of said signal pairs, first letter meaning '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' or absence of signal and the second one meaning '"'"''"'"''"'"''"'"'unity'"'"''"'"''"'"''"'"' or presence of signal:

(ZZ) pair is corresponding to said element 0, (UU) pair is corresponding to said element 1, (ZU) pair is corresponding to said element a, (UZ) pair is corresponding to said element b.

6. Apparatus as claimed in claim 5 including at least one of its stages having rank other than 1 for which said selected coefficient is equal to said element 0 and in which said electronic means includes no connection between its first and second inputs and its other inputs and its outputs, a direct connection between its third input and first output and a direct connection between its fourth input and second output.

7. Apparatus as claimed in claim 5 including at least one of its stages having a rank differing from 1 for which said selected coefficient is equal to said element 1 and in which said electronic means includes a first and a second '"'"''"'"''"'"''"'"'EXCLUSIVE OR'"'"''"'"''"'"''"'"' logic circuit each one having a first and a second input and one output, a direct connection between first input of said electronic means and first input of said second logic circuit, a direct connection between second input of said electronic means and second input of said first logic circuit, a direct connection between third input of said electronic means and first input of said first logic circuit, a direct connection between fourth input of said electronic means and second input of said second logic circuit, a direct connection between said output of said first logic circuit and first output of said electronic means and a direct connection between said output of said second logic circuit and second output of said electronic means.

8. Apparatus as claimed in claim 7 including one of its stages having a rank diFfering from 1 for which said selected coefficient is equal to said element a and in which said electronic means includes a third, a fourth and a fifth '"'"''"'"''"'"''"'"'EXCLUSIVE OR'"'"''"'"''"'"''"'"' logic circuit each one having a first and a second input and one output, direct connections between first input of said electronic means and respectively first input of said third and fifth logic circuits, a direct connection between second input of said electronic means and a second input of said third logic circuit, a direct connection between third input of said electronic means and first input of said fourth logic circuit, a direct connection between fourth input of said electronic means and second input of said fifth logic circuit, a direct connection between said output of said third logic circuit and a second input of said fourth logic circuit, a direct connection between said output of said fourth logic circuit and first output of said electronic means and a direct connection between said output of said fifth logic circuit and second output of said electronic means.

9. Apparatus as claimed in claim 8 including one of its stages having a rank differing from 1 for which said selected coefficient is equal to said element b and in which said electronic means includes a sixth, a seventh and an eighth '"'"''"'"''"'"''"'"' EXCLUSIVE OR'"'"''"'"''"'"''"'"' logic circuit each one having a first and a second input and one output, direct connections between second input of said electronic means and respectively second input of said sixth and said seventh logic circuits, a direct connection between first input of said electronic means and first input of said sixth logic circuit, a direct connection between third input of said electronic means and first input of said seventh logic circuit, a direct connection between fourth input of said electronic means and second input of said eighth logic circuit, a direct connection between said output of said sixth logic circuit and first input of said eighth logic circuit, a direct connection between said output of said seventh logic circuit and said first output of said electronic means and a direct connection between said output of said eighth logic circuit and said second output of said electronic means.