MEMORY PROTECTING CIRCUIT

• US 3,562,555 A
• Filed: 09/01/1967
• Issued: 02/09/1971
• Est. Priority Date: 09/01/1967
• Status: Expired due to Term

• Current Assignee: Richard W. Ahrons
• Original Assignee: Richard W. Ahrons
• Inventors: Ahrons, Richard W.
• Application Number:
  US04/665,126
• Time in Patent Office: 1,257 Days
• US Class Current: 365/229
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/002 protecting against parasitic influences, e.g. noise, temperatures
• CPC Class Codes: G06F 11/16 Error detection or correction of the data by redundancy in hardware
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A circuit for monitoring the power supply for a memory system which is arranged to inhibit operation of the memory system during a power supply failure while maintaining a temporary supply of power to the memory system.

Claims

1. A circuit comprising a transistor having a base, emitter and collector, an input terminal arranged to be connected to a power supply, first circuit means connecting said emitter to said terminal, a first output terminal, second circuit means connecting said vase to said output terminal, a second output terminal, third circuit means connecting said collector to said second terminal, a resistor connected between said collector and a point of reference potential, and a source of emergency power connected to said first output terminal and operative upon a fault of said power supply to reverse bias the emitter-base junction of said transistor while supplying power to said first output terminal, said source comprising a battery and a diode connected in series with the battery and poled to allow current flow from said battery.

2. A combination cOmprising a transistor having a base, emitter and collector, an input terminal arranged to be connected to a power supply, first circuit means connecting said emitter to said terminal, a first output terminal, second circuit means connecting said base to said first output terminal, a volatile memory system, means connecting said output terminal to said memory to supply power thereto, a second output terminal, third circuit means connecting said collector to said second terminal, a resistor connected between said collector and a point of reference potential, a signal-gating means operative to control the operation of said memory and fourth circuit means connecting said second output terminal to said gating means to apply a control signal thereto derived from a voltage across said resistor.

3. A combination as set forth in claim 2 and including a source of emergency power connected to said first output terminal which source is operative upon a fault of said power supply to supply power to said memory system.

4. A combination as set forth in claim 3 wherein said source is a capacitor.

5. A combination comprising memory means, a first power supply means for said memory means, switching means arranged to normally connect said first power supply means to said memory means, a second power supply means for said memory means, means responsive to a proper operation of said first power supply and operative upon an improper operation thereof to operate said switching means to disconnect said first power supply means from said memory means and to supply power to said memory means, memory-addressing means for addressing said memory means, and inhibit means responsive to a disconnect operation of said switching means by said second power supply means to inhibit said memory-addressing means to prevent further addressing of said memory.

6. The combination as set forth in claim 5 wherein said switching means includes a transistor having a base-emitter junction providing a current path between said memory means and said first power supply means.

7. The combination as set forth in claim 6 wherein said second power supply means includes a capacitor arranged to back-bias said emitter-base junction upon the failure of said first power supply means.

8. The combination as set forth in claim 6 wherein said switching means includes a resistor connected between a collector of said transistor and a point of reference potential and said inhibit means includes gating means responsive to a signal developed across said resistor.