REGENERATIVE FET SOURCE FOLLOWER

• US 3,564,290 A
• Filed: 03/13/1969
• Issued: 02/16/1971
• Est. Priority Date: 03/13/1969
• Status: Expired due to Term

• Current Assignee: George Sonoda
• Original Assignee: George Sonoda
• Inventors: Sonoda, George
• Application Number:
  US04/807,782
• Time in Patent Office: 705 Days
• US Class Current: 327/427
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence

Abstract

This specification describes a logic circuit having a capacitor coupled between the gate and source of an FET to cause the potential at the gate to follow the potential at source. The charge of this capacitor is controlled to render the FET conductive or nonconductive so that pulses applied to the drain of the FET can be selectively gated or not gated through the FET to a load connected to the source of the FET. By operating the FET in this way small supply voltages may be used. These voltages can be in the order of the size of the signals transmitted to the load.

Claims

1. A gating circuit comprising:

a. an FET device having a gating terminal and two gated terminals;

b. pulsing means for the application of a drive pulse to the first of the gated terminals;

c. a load connected to the second of the gated terminals;

d. biasing means for impressing a biasing potential on the gating terminal prior to the application of the drive pulse to the first of the gated terminals; and

e. capacitive feedback means coupling the gating terminal to the second of the gated terminals to bias the FET device conductive to said drive pulse by retaining charge from biasing potential and by regeneratively feeding the potential at the second of the gated terminals to the gating terminal.

2. The gating circuit of claim 1 including discharging means for selectively discharging the charge retained by the capacitor feedback means after the biasing potential has been applied to the gate but prior to the application of the drive pulse to the first of the gated terminals.

3. The gating circuit of claim 2 wherein said load is capacitive.

4. The gating circuit of claim 3 wherein said FET device is an enhancement mode metal oxide semiconductor field effect transistor.

5. A gating circuit comprising:

a. a source of drive pulses;

b. a load;

c. a first FET coupling the load to the source of drive pulses through its source to drain path;

d. a capacitor coupling the load to the gate of the first FET;

e. a source of biasing potential for charging the capacitor;

f. a second FET coupling the source of biasing potential to the gate of the first FET through the source to drain path of the second FET and the load;

g. a third FET forming a discharging path for the capacitor through the source to drain path of the third FET and the load;

h. set means for rendering the second FET conductive and then nonconductive prior to the application of a drive pulse to charge the capacitor and thereby render the first FET conductive; and

i. input means for selectively rendering the third FET conductive and nonconductive after the capacitor has been charged by the set means but prior to the application of the drive pulse to render the first FET nonconductive.

6. The gating circuit of claim 5 wherein the load is a capacitor.

7. The gating circuit of claim 6 wherein the first second and third FETS are enhancement mode metal oxide semiconductor field effect transistors.

8. In a circuit for transmitting a drive pulse from a source of pulses to an output load through the drain to source path of an FET, the improvement which comprises:

a. a capacitor coupling the gate of the FET to the output load side of the drain to source path of the FET; and

b. biasing means for providing a charging path to charge the capacitor prior to the transmission of the drive pulse and for supplying a high impedance path during the transmission of the drive pulse whereby the capacitor is initially charged to bias the FET conductive and then regeneratively feeds back to the gate the potential on the load side of the drain to source path to maintain the FET conductive.

9. The circuit of claim 8 including discharging means for providing a path to selectively discharge the capacitor in response to input signals occurring after the charging of the capacitor through the biasing means but prior to the drive pulse.

10. The circuit of claim 8 wherein said load is capacitive.

11. The circuit of claim 3 wherein said FET is an enhancement mode metal oxide semiconductor field effect transistor.