METHOD AND DEVICES FOR CONVERTING CODED BINARY SIGNALS INTO MULTILEVEL SIGNALS AND FOR RECONVERTING THE LATTER INTO THE FORMER

• US 3,569,955 A
• Filed: 10/11/1968
• Issued: 03/09/1971
• Est. Priority Date: 10/12/1967
• Status: Expired due to Term

• Current Assignee: Maurice A. Maniere
• Original Assignee: Maurice A. Maniere
• Inventors: Maniere, Maurice A.
• Application Number:
  US04/766,823
• Time in Patent Office: 879 Days
• US Class Current: 341/56
• CPC Class Codes: H04L 25/4919 using balanced multilevel codes H04L25/4927 takes precedence

Abstract

Code converter for converting a first sequence of coded binary signals xeach of said signals being formed of m bits, having a given duration and being capable of taking 2m possible values, into a second sequence of multilevel signals zn whose amplitude has (2m 1- 1) possible levels proportional to the series of integers from - (2m- 1) to + (2m- 1) including zero. The converter comprises a register for supplying the signals xn of the first sequence, a modulo p adder circuit where p 2m having a first input connected to the register and a second input, said modulo p adder circuit generating a third sequence of m-bit binary signals yn, a nonborrow subtractor circuit having a first input being connected to the output of said adder circuit and a second input, a delay circuit having an input connected to the output of the adder circuit for delaying said signals yn by the duration of the signals xn and thereby delivering the signals yn1 at the time of occurence of the signal xn and an output connected to the second input of both said adder circuit and subtractor circuit. The nonborrow subtractor circuit provides a sequence of m-digit signals whose digits are - 1, 0 and + 1. Each digit of said m-digit signals is multiplied by a coefficient equal to the weight thereof to obtain multilevel components relative to each of said digits and these components are algebraically added. Means for reconverting the multilevel signals zn into the coded binary signals xn are also described.

Claims

1. A process for converting a first sequence of coded binary signals xn, each of said signals being formed of m bits, having a given duration and being capable of taking 2m possible values, into a sequence of multilevel signals zn whose amplitude has (2m 1-1) possible levels equal to the series of integers from -(2m-1) to +(2m-1) including zero, and for reconverting said signals zn into said signals xn, said process comprising a first main step of deriving from the first sequence of signals xn, a second sequence of coded binary signals yn having m bits related to the signals xn by the relationship;

yn xn + yn 1 modulo p with p 2m said first main step including a first partial step of delaying the signals yn by the duration of the signals xn for obtaining the signal yn 1 and the second partial step of adding with modulo p the signals xn and yn 1, a second step of analogically subtracting the m-bit signals yn and yn 1 thereby obtaining resulting m-bit signals the digits of which are -1, 0 and +1 and a third step of translating said resulting m-bit signals the amplitude of which is equal to the binary value of said m-bit signals;

said reconverting process including a first step of detecting the sign of the signals zn, a second step of adding to those of the signals zn which are negative a signal whose amplitude represents the value 2m and a third step of translating into the binary code the amplitude of the positive signals zn and the amplitude of the negative signals zn increased by 2m.

2. A code converter for converting a first sequence of coded binary signals xn, each of said signals being formed of m bits, a(m 1)n, ...a2n, a1n, aOn, having a given duration and being capable of taking 2m possible values, into a second sequence of multilevel signals zn whose amplitude has (2m 1-1) possible levels equal to the series of integers from -(2m- 1) to +(2m- 1) including zero, comprising a m-stage register for supplying in parallel the digits of the signals xn of the first sequence, an m-stagE adder circuit having a first and a second set of m input terminals and a set of m output terminals, the input terminals of the first set receiving digits a(m 1),... a2n, a1n, aOn and the input terminals of the second set receiving the digits b(m 1)(n 1),... b2(n 1), b1(n 1), bO(n 1) of a signal yn 1 generated within the converter and the output terminals providing the digits b(m 1)n,... b2n, b1n, bOn to the exclusion of the digit bmn of a signal yn equal to the sum modulo p, where p 2m, of xn and yn 1, a nonborrow subtracter circuit having a first and a second set of m input terminals, the input terminals of the first set being respectively connected to the output terminals of said adder circuit, a delay circuit having a set of m input terminals respectively connected to the output terminals of said adder circuit for delaying the digits of the signals yn by the duration of the signals xn and thereby delivering the digits of the signals yn 1 at the time of occurrence of the digits of the signal xn and a set of output terminals connected to the input terminals of the second set of both said adder circuit and subtracter circuit, said nonborrow subtracter circuit providing a sequence of m-ternary-digit signals whose digits are -1, 0 and +1, means for multiplying each digit of said m-ternary-digit signals by a coefficient equal to the weight thereof and thereby obtaining multilevel components relative to each of said digits, and means for algebraically adding said multilevel components relative to the m digits of a signal.

3. A code converter for converting a first sequence of coded binary signals xn, each of said signals being formed of m bits, having a given duration and being capable of taking 2m possible values into a second sequence of multilevel signals zn whose amplitude has (2m 1-1) possible levels equal to the series of integers from -(2m-1) to +(2m-1) including zero, comprising a time base generating clock pulses, a first register controlled by said time base for supplying in parallel the bits of the signals xn of the first sequence, a modulo p adder circuit where p 2m having a first and a second input, the first input being connected to said register, said modulo p adder circuit generating a third sequence of m-bit binary signals xn, a nonborrow subtracter circuit having a first and a second input, the first input being connected to the output of said adder circuit, a second register having an input connected to the output of said adder circuit and an output, controlled by said time base synchronously with said first register and connected to the second input of both said adder circuit and subtracter circuit, whereby the signals yn are delayed by the duration of the signals xn, said nonborrow subtracter circuit providing a sequence of m-digit signals whose digits are -1, 0 and +1, means for multiplying each digit of said m-digit signals by a coefficient equal to the weight thereof and thereby obtaining multilevel components relative to each of said digits, and means for algebraically adding said multilevel components relative to the m-digits of a signal.

4. A code converter for converting a sequence of multilevel signals zn whose amplitude has (2m 1-1) possible levels proportional to the series of integers from -(2m-1) to +(2m-1) including zero into a sequence of coded binary signals xn, each of latter said signals being formed of m bits and having 2m possible values, comprising means for detecting the sign of the signals zn of the first sequence, adder means for adding only to those of the signals zn which are negative a signal whose amplitude is proportional to the value 2m and means for coding into the binary code the amplitude of the positive signals zn and the amplitude of the negative signals zn increased by a quantity proportional to 2m.