DECIMAL POINT PROCESSING APPARATUS

• US 3,571,808 A
• Filed: 12/06/1968
• Issued: 03/23/1971
• Est. Priority Date: 12/12/1967
• Status: Expired due to Term

• Current Assignee: Hanahara Hitoshi, Teramura Satoshi, Washizuka Isamu
• Original Assignee: Hanahara Hitoshi, Teramura Satoshi, Washizuka Isamu
• Inventors: WASHIZUKA ISAMU, TERAMURA SATOSHI, HANAHARA HITOSHI
• Application Number:
  US04/781,849
• Time in Patent Office: 837 Days
• US Class Current: 713/600
• CPC Class Codes: G06F 15/02 manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators
• CPC Class Codes: G06F 7/491 Computations with decimal numbers radix 12 or 20. G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/4981 Adding; Subtracting
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET

Abstract

A computer having registers in which a plurality of memory cells are connected in cascade in correspondence with the desired number of bits, only one of said memory cells is arranged to have an operational state different from those of all of the other memory cells and the bit location of said memory cell having the operational state (memory state) different from the others is caused to correspond to a numerical value to be stored, means of shifting said bit location of said memory cell having the operational state different from the others to another bit location, and shift control means for determining said bit location to which said bit location of said memory cell having the operational state different from the others is to be shifted in correspondence with a numerical value to be arithmetically operated as one operand with respect to said numerical value already stored in the register.

Claims

1. An operation device comprising registers each composed of cascade-connected memory cells the number of which corresponds to the predetermined number of bits and arranged that one of said memory cells located in a bit position relating to a numerical value to be stored takes an operational state different from those of the other memory cells, shift means connected to said registers for shifting the content of said memory cells taking the operational state different from the others to another memory cell located in another bit position, and shift control means connected to said shift means for deciding said another bit position to which the content of said memory cell taking the operational state different from the others is to be shifted in correspondence with an operand to be supplied for an arithmetic operation with respect to the numerical value already stored in one of said registers each of said memory cells being composed of at least two storage MOS type field effect transistors connected in cascade and arranged to store an information in a capacitor constituted between the gates and the substrates of said MOS type field effect transistors as an electrostatic charge.

2. Decimal point processing apparatus comprising at least two registers with one register storing numerical information and the other register storing information relating to the position of the decimal point in the numerical information stored in said one register, said other register including at least two transistors connected one to the other for storing one bit of said decimal point information, a generator for generating at least one set of timing signals having a time scale corresponding to the weight of the information and determining the boundaries of each word time, decimal point processing means including a plurality of logical gating circuits connected to said generator, connections between said decimal point processing means and said registers, said decimal point processing means modifying the information stored in the decimal point register in accordance with new decimal point information at the termination of each timing period, the modified decimal point information being delivered during a period of one timing signal within each word time, the time scale of the timing signal determining the decimal point position of the resulting information, and time sharing indicating means connected with said generator, the last said means including decimal point indicating elements interconnected one with the other and with said decimal point processing means and actuated by the decimal point information at a period of one timing signal during each work time.

3. Decimal processing apparatus according to claim 2 wherein said transistors are MOS field effect transistors connected in cascade and said one bit of decimal point information is capacitively stored in the capacitor formed between each gate electrode and the substrate of each transistor

4. Decimal point processing apparatus according to claim 2 wherein said time sharing indicating means includes a plurality of numerical indicating means.

5. Decimal point processing apparatus according to claim 2 wherein said decimal point processing means includes means for modifying the information stored in said decimal point register in accordance with the new decimal point information at the termination of each timing period.

6. Decimal point processing apparatus according to claim 5 wherein said decimal point processing means includes means for delivering the modified decimal point information during a period of one timing signal within each word time.