COMPUTER MEMORY PROTECTION

• US 3,573,855 A
• Filed: 12/31/1968
• Issued: 04/06/1971
• Est. Priority Date: 12/31/1968
• Status: Expired due to Term

• Current Assignee: Harvey G. Cragon, William J. Watson
• Original Assignee: Harvey G. Cragon, William J. Watson
• Inventors: Cragon, Harvey G., Watson, William J.
• Application Number:
  US04/788,166
• Time in Patent Office: 826 Days
• US Class Current: 711/163
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 13/12 using hardware independent of the central processor, e.g. channel or peripheral processor

Abstract

A data processing system is provided with a central processing unit with an arithmetic unit which is accessible to and from memory over buffered channels. The system is provided with registers for storage of upper and lower memory bounds for data to be read, data to be written and instructions to be fetched for execution. A comparison means is responsive to a request from memory for comparing each memory request with the bounds stored in the register file. The request from memory is enabled if the bounds comparison is satisfied, means being provided to elect internal or external bounds comparison.

Claims

1. Processor means including a memory to provide memory bounds protection for data to be read, data to be written and instructions to be fetched for execution from a memory which comprises:

a. an upper bounds and lower bounds register pair to store upper and lower memory addresses for each of read, write and execute memory storage addresses;

b. a source of memory request words including ID code bits, memory address bits and accommodation for data bits;

c. bounds comparators, one connected to each said pair of bounds registers for comparing said memory address bits with the upper and lower memory addresses of the connected upper and lower bounds register pair;

d. decode logic responsive to said ID code bits to select one of said bounds comparators; and

e. means responsive to the selected bound comparator to apply an enable bit to said memory if said memory address bits satisfy the selected comparator.

2. The combination of claim 1 wherein peripheral processor means are provided to vary the response of each said comparator means from internal to external bounds comparison.

3. A memory protect system for a computer having a CPU which transmits requests for access to memory by way of a memory control unit in the form of a word having memory access code bits, memory address bits and data bits, comprising:

a. bounds registers adapted to store upper and lower memory address bounds therein;

b. a comparator means for response to the stored bounds addresses in said registers;

c. means responsive to said memory access code bits for allowing said memory address bits to be applied to said comparator means for comparison with the upper and lower address bounds specified by said memory access code bits; and

d. means responsive to a predetermined bounds comparison in said comparator to enable an access to said memory at the memory address specified by said memory address bits.

4. The combination of claim 3 wherein means are provided to vary the response of said comparator from internal to external bounds comparison.

5. The combination set forth in claim 3 wherein there are three pairs of bounds registers in which read data address bounds, write date address bounds, and execute address bounds are stored, corresponding comparators are provided, and means are provided for providing first access code bits for a read access to memory, second access code bits for a write access to memory, and third access code bits for an execute access to memory.

6. The method of memory protection controlling access to memory of read, write, and execute memory requests, which comprises:

a. storing in memory predetermined data;

b. generating memory access code bits;

c. storing separately from said memory, upper bounds and lower bounds for each of read, write and execute memory storage addresses;

d. generating signals representative of requests of particular addresses in memory;

e. comparing the requested addresses with said bounds addresses specified by said memory access code bits; and

f. enabling said memory to respond to said request, if said comparison satisfies said upper and lower stored bounds specified by said memory access bits.

7. A memory protect system for a computer having a CPU which transmits requests to memory by way of a memory control unit in the form of a word having ID code bits, address bits and data bits, comprising:

a. peripheral processor means and bounds registers responsive to said peripheral processor means adapted to store upper and lower memory address bounds therein;

b. comparator means for response to the stored bounds addresses in said registers;

c. decode means having three output channels responsive to said ID code bits;

d. AND gates, one connected to each of said output channels and all connected to receive said address bits to apply said address bits to said comparator means for comparison with upper and lower address bounds specified by said ID code bits;

e. means responsive to a bounds comparison to enable a memory cycle including said address bits; and

f. means for varying the response of said comparison means from an internal to an external bounds comparison.

8. The combination set forth in claim 7 wherein each said comparator applies a signal indicating the denial of a memory request to said peripheral processor when any bounds comparison fails.