VARIABLE CONDUCTION THRESHOLD TRANSISTOR MEMORY CIRCUIT INSENSITIVE TO THRESHOLD DEVIATIONS

• US 3,579,204 A
• Filed: 03/24/1969
• Issued: 05/18/1971
• Est. Priority Date: 03/24/1969
• Status: Expired due to Term

• Current Assignee: Lincoln Andrew James
• Original Assignee: Lincoln Andrew James
• Inventors: LINCOLN ANDREW JAMES
• Application Number:
  US04/809,899
• Time in Patent Office: 785 Days
• US Class Current: 365/184
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence

Abstract

A memory circuit for application in a computer memory for storing a binary valued digit. The circuit comprises two insulated gate field effect transistors characterized by electrically controllable conduction thresholds established by potentials applied between the respective gate electrodes and substrates. A binary digit is stored by establishing a difference in threshold between the two transistors and is read by sensing the difference in current flow therebetween in response to an interrogation potential applied to the gate electrodes thereof. The binary value ONE or ZERO is stored by establishing a higher threshold for one transistor with respect to the other or for the other transistor with respect to the one.

Claims

1. A memory circuit comprising first and second variable threshold transistor means having source, drain and gate electrodes formed on substrates, respectively, said transistor means having electrically controllable conduction thresholds established by potentials having values above a certain magnitude applied between said gate electrodes and said substrates, writing means for applying a first potential between said gate electrode and said substrate of said first transistor means having a value above said magnitude to establish a first conduction threshold therefor, and for applying a second potential between said gate electrode and said substrate of said second transistor means having a value above said magnitude to establish, for said second transistor means, a second conduction threshold different from said first conduction threshold, reading means for applying an interrogation potential to said gate electrodes of said first and second transistor means having a value below said magnitude, biasing means for biasing said source and drain electrodes of said first and second transistor means, and comparison means for comparing the current flowing through said source and drain electrodes of said first transistor means with the current flowing through said source and drain electrodes of said second transistor means in response to said interrogation potential.

2. A memory circuit of the character recited in claim 1 wherein the difference between said thresholds is sufficient to enable current flow through said source and drain electrodes of said first transistor means to differ from current flow through said source and drain electrodes of said second transistor means by At least a predetermined amount when both said transistor means are conducting.

3. A memory circuit of the character recited in claim 2 wherein said value of said interrogation potential is effective to establish current flow of at least said predetermined amount through the source and drain electrodes of one of said transistor means when said first and second thresholds are established.

4. A memory circuit of the character recited in claim 3 wherein said writing means is adaptable for applying said first and second potentials to said first and second transistor means respectively or to said second and first transistor means respectively, to selectively enable current flow through said first or second transistor means to exceed current flow through said second or first transistor means respectively by said predetermined amount in response to said interrogation potential.

5. A memory circuit of the character recited in claim 4 in which said first and second transistor means are fabricated on a slice of semiconductor material, said memory circuit further includes a plurality of pairs of variable threshold transistor means fabricated on said slice, and said memory circuit also includes additional writing means, reading means, biasing means and comparison means for providing respectively writing potentials, interrogation potentials, biasing potentials and comparison functions for said pairs of variable threshold transistor means.