DIGITAL CAPACITANCE METER BY MEASURING CAPACITOR DISCHARGE TIME

• US 3,581,196 A
• Filed: 10/28/1968
• Issued: 05/25/1971
• Est. Priority Date: 10/28/1968
• Status: Expired due to Term

• Current Assignee: William L. Spaid
• Original Assignee: William L. Spaid
• Inventors: Spaid, William L.
• Application Number:
  US04/771,026
• Time in Patent Office: 939 Days
• US Class Current: 324/678
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: H03M 1/50 with intermediate conversion to time interval H03M1/64 takes precedence

Abstract

A fully automatic capacitance meter with decimal readout. The meter operates cyclically at a relatively high frequency, acting in an initial small fraction of each cycle to charge the unknown capacitor to a predetermined voltage, discharge the capacitor at a constant rate to zero voltage, measure the time interval required for discharge to produce a time analog of the capacitance, and convert the time analog to a decimal number. The remaining large fraction of each cycle is used to display the decimal number. Automatic range switching is accomplished by changing the discharge rate.

Claims

1. A digital capacitance meter comprising:

means for charging an unknown capacitor to a known voltage;

means including a constant current source for discharging said capacitor from said known voltage to a predetermined voltage lower than said known voltage at a constant predetermined rate;

means for determining the interval of time required for said discharge to occur; and

means for producing a numerical representation of said interval of time.

2. A digital capacitance meter comprising:

means for charging an unknown capacitor to a known voltage;

means including a constant current source for discharging said capacitor from said known voltage to a predetermined voltage lower than said known voltage at a constant predetermined rate;

means for determining the interval of time required for said discharge to occur;

a source of pulses having a constant repetition rate;

a counter for counting the number of said pulses occurring during said time interval;

means for displaying the count in said counter;

mean for operating said capacitance meter cyclically; and

range changing means coupled to said counter and to said constant current source an operative immediately following the occurrence of a full count in said counter to increase the value at which the discharge current is held constant.

3. Apparatus as claimed in claim 2 in which said constant current source comprises:

a transistor the collector current of which is the dischaRge current of said capacitor, an emitter resistor in the emitter circuit of said transistor, a high gain circuit receiving the voltage across said emitter resistor as an input for controlling the base-emitter voltage of said transistor in such direction as to oppose any change in the emitter current and consequently in the collector current of said transistor; and

in which said range changing means comprises;

a plurality of taps, equal in number to the number of ranges, on said emitter resistor;

separate normally open short circuiting means connected between each tap and one end of said resistor, the values of resistance between taps decreasing from said one end as required for the resistance of the unshorted portion of the resistor remaining after each shorting means is closed in succession, starting with the shorting means connected to the tap nearest the said one end of the emitter resistor, to be a fixed fraction of the resistance of the unshorted portion of the resistor before the shorting means closed; and

means coupled to said counter and to said shorting means and operative immediately following the occurrence of each full count in said counter to close said shorting means in said succession.

4. Capacitance measuring apparatus comprising:

terminals A and B between which an unknown capacitor may be connected;

means providing a point of predetermined constant direct potential relative to a point of reference potential;

a resistor connected between terminal A and said constant potential point;

a diode connected between terminal B and said point of reference potential, said diode completing a charging circuit for said unknown capacitor between said point of constant potential and said point of reference potential and being poled so as to have its forward direction correspond to the direction of charging current flow;

a two terminal source of direct current having one terminal connected to said point of reference potential;

a constant current device connected between the other terminal of said direct current source and terminal B, said source and constant current device being poled to send current through said diode in the forward direction;

a voltage comparator connected to terminal B and to said point of reference potential for comparing the potential of terminal B with said reference potential and producing an output voltage having one of two possible levels when the potential of terminal B is below the reference potential and the other of the two possible levels when above the reference potential; and

means for connecting terminal A to said point of reference potential for a predetermined period, the duration of the rectangular pulse at the output of said comparator resulting from output level transitions during said period being the time analog of the capacitance of said unknown capacitor.

5. Apparatus as claimed in claim 4 and in addition:

a source of pulses having a constant repetition rate;

an AND gate to which said pulses and the output of said voltage comparator are applied as inputs;

a counter coupled to the output of said AND gate for counting the number of pulses passing the gate;

storage means coupled to said counter for storing the count;

means coupled to the storage means for providing a numerical display of the stored count;

means generating a periodic rectangular wave (o) having in each cycle an initial portion at one voltage level followed by a final portion at another voltage level, said initial portion being a small fraction of the total period of the cycle;

means applying said wave (o) to said storage means for controlling its operation such that during the said first portion of said wave the storage means follows the count in the counter and during the said final portion stores the count that was present in the counter when the transition between first and second portions occurred;

means generating a plurality of successive equally spaced rectangular pulses (k) during the first portion of each cycle of wave (o);

means generating a number of equally spaced (a) pulses equal to the number of (k) pulses and each occurring after its corresponding (k) pulse;

means applying said (k) pulses to said counter for resetting the counter to zero at each pulse;

means applying said (a) pulses to the said means for connecting terminal A to said point of reference potential for effecting said connection for the duration of each (a) pulse;

a plurality of bistable circuits each having a first and second stable states coupled to said constant current device for controlling the value at which the current is held constant, the arrangement being such that when all circuits are in their first state the current has its lowest value and actuation of said circuits to their second states successively in a prescribed order increases the current by a predetermined factor for each actuation;

means for applying the first (k) pulse to occur in each cycle of said wave (o) to said bistable circuits for resetting them to their said first states; and

means coupled to said counter and operative immediately after each full count to set said bistable circuits to their said second states, one for each full count and in said prescribed order.

6. Apparatus as claimed in claim 5 in which said constant current device comprises a transistor having its collector connected to said B terminal and its emitter connected through an emitter resistor to said source of direct current, and a high gain circuit receiving the voltage across said emitter resistor as an input for controlling the base-emitter potential of said transistor in such direction as to oppose any change in the emitter current and consequently in the collector current of said transistor;

a plurality of taps, equal in number to the number of said bistable circuits, on said emitter resistor;

separate normally open short circuiting means connected between each tap and one end of said resistor, the values of resistance between taps decreasing from said one end as required for the resistance of the unshorted portion of the resistor remaining after each shorting means is closed in succession, starting with the shorting means connected to the tap nearest the said one end of the emitter resistor, to be a fixed fraction of the resistance of the unshorted portion of the resistor before the shoring means was closed; and

couplings between said bistable circuits and said shorting means for closing the shorting means when the associated bistable circuit is in its said second stable state.