ALPHANUMERIC,VARIABLE WORD LENGTH,CHANNEL SCANNING SELECTIVE SIGNALLING SYSTEM

• US 3,585,598 A
• Filed: 07/24/1969
• Issued: 06/15/1971
• Est. Priority Date: 07/24/1969
• Status: Expired due to Term

• Current Assignee: Dormer Keith Henry, Dowling Edward Camp, Hudson William Jeffrey Jr, Yaccino Michael Joseph
• Original Assignee: Dormer Keith Henry, Dowling Edward Camp, Hudson William Jeffrey Jr, Yaccino Michael Joseph
• Inventors: HUDSON WILLIAM JEFFREY JR, YACCINO MICHAEL JOSEPH, DOWLING EDWARD CAMP, DORMER KEITH HENRY
• Application Number:
  US04/847,797
• Time in Patent Office: 691 Days
• US Class Current: 455/112
• CPC Class Codes: H04W 88/185 Selective call encoders for paging networks, e.g. paging centre devices

Abstract

A communication system for selective signalling between remote stations is disclosed which features an encoder capable of generating trains of binary bits representative of alphanumeric symbols and converting such bits into mark and space tones or signals for transmission. The encoder includes data register binary memory stages to temporarily store a calling code in serial bit form and logic is provided to permit recirculation of the code for redundant transmission. The encoder stages are coupled and driven to accommodate variable length calling codes with a character register controlled by a memory register to index the data register for such purpose. A receiver-decoder is provided to detect the transmitted mark-space code and convert such into a binary train in proper time relationship. The decoder includes a programmable input to a single eight stage register to generate a local code and Exclusive-OR logic to compare incoming detected code bits with generated code bits and provide a success detect output upon receipt of a proper code. The generation of a local code is used to provide an auto-acknowledge call from the receiver. The receiver includes circuit logic to optimize detection of proper codes and rejection of improper codes or spurious signals. A multichannel scanner is provided in conjunction with the receiver-decoder to automatically search for incoming codes on different channels and logic is provided to perform a number of output command functions responsive to a proper calling code.

Claims

1. In a system for selective signalling, input means including a keyboard operable for selectively generating a binary bit representation of one of a plurality of alphanumeric characters forming a calling address code, first bistable storage means responsive to said input means cApable of being set into a stable condition to store said generated bits in series for forming a calling address code message in conjunction with other selector characters and logic means connected to said first storage means for effecting a serial output of the stored bits for transmission and simultaneously routing of said stored bits back into said first storage means, send means operable to initiate said logic means to effect said transmission, said logic means including a separate second storage means for storing an indication of the number of characters in a message and automatically operable to position the routed bits in said first storage means for retransmission, permitting transmission of an address code message any number of times and permitting transmission of messages of variable character composition and character number.

2. The system of claim 1 further including delay means responsive to said send means for providing a controlled interval prior to output of the first of plural bits representing a first character of said calling address code message and means for generating a nonmessage calling character in binary bit form during said interval for operating receiver equipment preparatory to reception of said message.

3. The system of claim 1 including indicating means operable in response to the storage of said bits in said first storage means for indicating which bit representation of characters of a certain predetermined number of bit representations of characters is stored preparatory to transmission.

4. The system of claim 1 including a driver for advancing said bits representing characters serially along said first storage means, means for gating said driver on after the input of a character into said first storage means and means responsive to a predetermined condition in said separate second storage means which in turn is responsive to said first storage means to gate said driver off.

5. In a system for selective signalling, input means including a keyboard generating any one of a plurality of characters, each formed of a pattern of binary bits, a data register including a plurality of bistable stages connected for serial transfer of characters, a first group of said stages connected to said input means to be simultaneously set by a pattern of bits to form a character in said data register, a character register including a plurality of bistable stages connected for serial transfer with a binary bit stored in only one of said stages, means connected to drive said data register and said character register for advancing characters from stage-to-stage in said data register to form a stored message and including means for advancing said bit in said character register to indicate the number of characters in said data register, and means for energizing said drive means to effect an output of said characters from said data register for transmission, the character register being reset simultaneously with said output of said characters to indicate a zero character count.

6. The system of claim 5 wherein said character register includes plural stages, each with an output terminal, with an output from one of said stages provided by the presence of a bit in said one of said stages indicative of the number of characters stored in said data register.

7. The system of claim 5 wherein there is included memory register means including a plurality of bistable stages connected for transfer of a binary bit stored therein, said memory register means having an input connection from the stages of said character register to store the character count therein, logic means responsive to a predetermined condition of said memory register for controlling said driver means to effect a drive to advance the characters forming the transmitted message into a proper position in said data register in accordance with message length and means for feeding said message back into said data register as the message is being output for transmission.

8. An encoder for generatinG codes comprised of a series of binary bits forming characters, comprising input means generating a group of bits as a pattern forming a character, a data register including a plurality of serially coupled stages, each stage containing a plurality of bit storage elements to store a single character one of said stages being connected to said input means for receiving a character input, driver means for advancing characters set into said one stage along said data register, a character register having a bit storage element for a majority of the stages in the data register, an output from each said element being energized by introduction of a binary bit therein which is advanced along said character register under drive from said drive means, said output serving to simultaneously provide an indication of the number of characters stored in said data register and including means through a connection to said driver for providing an automatic advance of characters to permit serial loading of characters in said data register.

9. In a selective signalling system, a calling station including an encoder having means to selectively provide input of any one of a predetermined plurality of characters in the form of binary bits, register means including binary bit positions connected for serial transfer, drive means to drive said register means to create an output of said bits and means to convert said binary bits into mark and space pulses of a given time duration, a plurality of called stations each having a receiver including a decoder having different characteristics of response relative to different messages formed of characters, each said receiver including a further register means having bit positions in number equal to the number of bits in a given character, means to stop said further register, means to decode a series of distinct characters one character at a time in said further register when said further register is stopped and means for producing an output at a receiver only if all characters of a given transmitted message are successfully decoded so as to provide an indication of call only at stations uniquely associated with the given message.

10. In a selective signalling system, an encoder operable to generate a series of time defined characters as a calling message code and a receiver adapted to receive said message, said receiver including decoder means to decode one character at a time and means to successively set said decoder means for each of a series of characters to be decoded, means to disable said decoder means in the event that a given character is not decoded within the time definition for a character, to reset said receiver and block an indication of call, and indication means responsive to a successful decoding of all characters in a calling message to provide an output indicating that the receiver is being called.

11. The system of claim 10 wherein said system further includes a plurality of receiver channels wherein said encoder time defined characters are mark and space signals and said receiver includes a plurality of timers which sense the presence of a mark signal or a space signal and means responsive to said timers for developing control signals in the event the presence of such signals exceed a predetermined time duration, said receiver further including channel scanning means responsive to said control signals for causing said scanning means to step to a different one of said channels.

12. The system of claim 11 wherein said receiver includes a further timer operable in response to the absence of either mark or space signals to develop a series of control pulses for operating said scanning means at said receiver station.

13. In an apparatus for scanning a plurality of different receiver channels, a receiver including means to sense the presence or absence of a distinct message format signal for given periods of time and operable to produce first and second control signals, respectively, in response to said sensing, channel scanning meAns including a series of gates each having a different channel input and an output connected to said receiver, channel stepping means responsive to said second signal for sequentially operate said gates to cause said receiver to look for a signal input and including means responsive to said second signal for holding the gate then operated closed to provide a continuous input to said receiver, said receiver including means operable in response to a given message format to produce a third signal for inhibiting said channel stepping means indefinitely from sequentially operating said gates and including means operable in response to the message format for produce a fourth signal causing said channel stepping means to again sequentially operate said gates.

14. The system of claim 13 wherein said channel stepping means is a binary counter operable to generate a binary code and there is included a logic circuit having outputs to said gates and responsive to said code to selectively operate said gates.