WELDING CONTROL MECHANISM

• US 3,586,815 A
• Filed: 03/26/1969
• Issued: 06/22/1971
• Est. Priority Date: 03/26/1969
• Status: Expired due to Term

• Current Assignee: Eijnsbergen Jacobus Van, O'Neal George Jr
• Original Assignee: Eijnsbergen Jacobus Van, O'Neal George Jr
• Inventors: EIJNSBERGEN JACOBUS VAN, O'NEAL GEORGE JR
• Application Number:
  US04/810,499
• Time in Patent Office: 818 Days
• US Class Current: 219/90
• CPC Class Codes: B23K 11/245 using a stepping counter in synchronism with the welding pulses electromagnetic counters G06M
• CPC Class Codes: B23K 11/256 the measured parameter being the inter-electrode electrical resistance

Abstract

A control circuit which is particularly adapted to be utilized in conjunction with a welding circuit wherein the voltage across the welding electrodes and the current through the work is sensed for a variable period of time which is related to the magnitude of the current. These signals are then utilized to derive the resistance of the load or the work being welded, the system being capable of automatically terminating the weld when a preselected degree of resistance drop at the weld is sensed by the feedback control circuit.

Claims

1. In a timing circuit for a welding system of terminating the weld portion of a welding cycle in response to a variation in the resistance of the work at the weld electrodes comprising means for Sensing a first and second electrical characteristic at the weld electrodes, variations in said characteristics providing an indication of the resistance and other variations of said welding system, means for generating an electrical signal in response to variations in the resistance and eliminating said other variations including means for sensing said characteristics and sampling said first characteristic during a variable sample time and means for varying said sample time in response to variations in one of said first and second characteristic.

2. The improvement of claim 1 wherein said characteristics include the voltage across the electrodes and the current through the work.

3. The improvement of claim 1 wherein said generating means includes chargeable means having an output signal of a magnitude related to the resistance.

4. The improvement of claim 3 wherein a charging voltage directly related to said voltage is applied across said chargeable means and said variable sampling time determines the charging time of said chargeable means.

5. The improvement of claim 4 wherein said sample time is inversely related to the magnitude of the current through the work.

6. The improvement of claim 5 wherein said generating means includes gate means connected between said voltage sensing means and said charging means, said gate means being enabled during said sampled time.

7. The improvement of claim 6 wherein further including means for initiating said sample time when said current is at a peak and the rate of change of current with respect to time is approximately zero.

8. The improvement of claim 6 wherein said gate means includes a diode junction connected between the voltage sampling circuit and the chargeable means.

9. The improvement of claim 8 wherein said diode junction is a two-terminal device.

10. The improvement of claim 9 wherein said gate means further includes a second diode junction connected in series with said first diode junction, the conduction of said second diode junction causing said first diode junction to eliminate the voltage signal from the point between said voltage sensing means and said chargeable means.

11. The improvement of claim 10 wherein said second diode junction is rendered forward biased during said sample time.

12. The improvement of claim 11 wherein said current sampling means includes means for rectifying alternating current portions of said current, said sampling time being varied in accordance with the amplitude of said rectified current.

13. The improvement of claim 12 wherein said current sensing means further includes polarity reversing means and biasing means, said biasing means being of a value to permit peaks of said rectified, reversed current to provide a baising voltage to control the sampling time, the sampling time varying as a function of the time said rectified, reversed current provides said biasing voltage.

14. The improvement of claim 13 wherein said sampling time varies as an inverse function of the amplitude of said rectified current.

15. The improvement of claim 14 further including resistance comparison circuit means including means for storing the maximum value of said resistance and means for sensing the instantaneous value of said resistance.

16. The improvement of claim 15 wherein said comparison circuit means includes a voltage responsive circuit for at least a first and second electrode, said stored resistance being fed to one of said first and second electrodes, and said instantaneous resistance being fed to the other of said electrodes, said voltage response circuit generating an output signal when said stored resistance signal and said instantaneous resistance signal bear a preselected relationship, one to the other.

17. The improvement of claim 16 wherein said preselected relationship is a preselected difference between said signals.

18. The improvement of claim 17 further including bistable storage means having a first and second state, said bistable storagE means being switched from said first to said second state in response to said stored resistance and said instantaneous resistance signals achieving said preselected difference.

19. The improvement of claim 18 wherein said bistable storage means initiates and terminates the portion of a weld cycle, said storage means being switched to said first state to initiate said weld portion and being switched to second state to terminate said weld portion.

20. The improvement of claim 19 further including minimum weld portion time sensing circuit, said minimum time sensing circuit including means for sensing the initiation of said weld portion and means for timing a preselected duration for said minimum time.

21. The improvement of claim 20 wherein said minimum time sensing circuit inhibits the switching of said bistable storage means from said first to said second state prior to the timing of said minimum time.

22. The improvement of claim 21 wherein said bistable storage means includes an output amplifier and a flip-flop circuit.