EXPANDER FOR REAL-TIME COMMUNICATION BETWEEN A COMPUTER AND EXTERNAL DEVICES

• US 3,597,743 A
• Filed: 03/26/1969
• Issued: 08/03/1971
• Est. Priority Date: 03/26/1969
• Status: Expired due to Term

• Current Assignee: Alan S. Rosenthal, William J. Murphy
• Original Assignee: Alan S. Rosenthal, William J. Murphy
• Inventors: Murphy, William J., Rosenthal, Alan S.
• Application Number:
  US04/810,521
• Time in Patent Office: 860 Days
• US Class Current: 710/2
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

A device is described for expanding the real-time access channel of a digital computer to enable the computer to communicate with a large number of external devices. A plurality of channels are arranged in groups, with each group forming a feature adapter. A plurality of feature adapters are shown connectable to the computer. A controller provides the necessary control functions to manipulate the data which may be sent to or demanded from the computer on an interrupt request basis or under direct program control.

Claims

1. An expander for a digital computer real time access channel for real time communication with a plurality of devices located external to the computer, comprising a plurality of feature adapters composed of a plurality of channel data lines coupled to external devices and control gates which selectively interconnect the channel data lines in the feature adapters to the real time computer access channel. controller means for directing the flow of data between the real time computer access channel and said channel data lines, said controller means including:

means actuated by an external device for generating an interrupt signal to the computer, means responsive to interrupt signals from devices coupled to a predetermined feature adapter group of data lines for storing said interrupt signals, means responsive to said predetermined group of stored interrupt signals for generating said interrupt signals at preselected computer determined interrupt levels, means responsive to a computer interrupt response inquiry signal for supplying to the computer a signal to identify the interrupting external device.

2. The device as recited in claim 1 wherein the controller means further includes:

means responsive to selected bits in the computer access channel for identifying the computer interrupt response inquiry signal and generating a signal indicative thereof, means responsive to the interrupt response inquiry signal for coupling the stored interrupt signal to the computer access channel at a preselected bit location thereof for the identification of the interrupting device.

3. The device as recited in claim 2 wherein said controller means further includes:

means responsive to a first computer interrupt response inquiry signal for identifying to the computer the feature adapter group of data lines from where the interrupt signal was generated, and means rEsponsive to a second computer interrupt response inquiry signal for identifying the particular channel data lines associated with the interrupting device.

4. The device as recited in claim 3 wherein said means responsive to the second computer interrupt response inquiry signal further includes means responsive to preselected output bits from the computer access channel for decoding a feature adapter signal representative of the group of data lines causing an interrupt, and means actuated by the feature adapter signal for generating an interrupt status signal representative of the particular device connected to data lines in the group causing the interrupt and coupling the interrupt status signal to a predetermined bit of the computer access channel at a predetermined time.

5. An expander for a digital computer real time access channel for real time communication with a plurality of devices located external to the computer comprising a plurality of feature adapters composed of a plurality of channel data lines coupled to external devices and control gates which selectively interconnect the channel data lines in the feature adapters to the real time computer access channel, controller means for directing the flow of data between the real time computer access channel and said channel data lines, said controller means including:

means for generating an interrupt signal to the computer from external devices, means responsive to interrupt signals from external devices which are coupled to a predetermined feature adapter group of data lines for storing said interrupt signals, means responsive to said stored interrupt signals for generating said interrupt signals at preselected computer determined interrupt levels, means responsive to selected bits in the computer real time access channel for identifying a computer interrupt response inquiry signal and generating a signal indicative thereof, means responsive to a first identified interrupt response inquiry signal for coupling the stored interrupt signals to preselected bit locations of the computer access channel for identification to the computer of the feature adapter group of data lines from where an interrupt signal was generated, means responsive to a second identified computer interrupt response inquiry signal for generating an interrupt status signal identifying the particular external device connected to the feature adapter group of data lines causing the interrupt and coupling the interrupt status signal to a predetermined bit of the computer access channel at a predetermined time, means responsive to a preselected bit location in the computer access channel and actuated by the first computer interrupt response inquiry signal for generating an interrupt clearing signal for selectively clearing the stored interrupt signal upon complete identification of the device causing the interrupt.

6. The device as recited in claim 5 wherein said controller means further includes:

means responsive to selected bits in the computer access channel for decoding a signal representative of the second computer interrupt response inquiry, means enabled by said second interrupt response inquiry signal and responsive to a selected bit in the computer access channel for generating a clearing interrupt signal for removing the stored interrupt upon complete identification of the device causing the interrupt.

7. An expander for a digital computer real time access channel for real time communications with a plurality of devices located external to the computer comprising:

a plurality of feature adapters composed of a plurality of channel data lines coupled to external devices and control gates which interconnect the channel data lines in the feature adapter to the real time computer access channel controller means for directing the flow of data between the real time computer access channel and said channel data lines, said controller means including meaNs actuated by an external device for generating an interrupt signal to the computer, means responsive to a computer interrupt response inquiry signal for supplying to the computer a signal to identify the interrupting external device, an analog-to-digital converter coupled by a feature adapter to the real time access channel and having a conversion initiating input and providing a busy indicating output signal, said converter converting an analog parameter signal from an external device, means actuated by the busy signal for producing an interrupt signal to the computer, storage means for storing said interrupt signal, and means for clearing said storage means at a preselected time after transfer of converted data from the analog-to-digital converter to the computer.

8. The device as recited in claim 7 and further including:

amplifier means for amplifying the analog parameter signal prior to analog-to-digital conversion, and means controlled by preselected bits in the computer real time access channel for varying the gain of said amplifier means.

9. The device as recited in claim 8 wherein said gain varying means further comprises:

storage flip-flops coupled to the selected gain setting bits, decode means coupled to the flip-flops and providing a plurality of gain control signals, and means responsive to the decoded gain control signals for inserting corresponding gain varying resistances in the amplifier means.

10. The device as recited in claim 9 wherein the gain resistance varying means comprises a plurality of relays actuated by the gain control signals and a plurality of switches, each controlled by a relay, and gate means for selectively altering the bit information placed in said storage flip-flops.

11. The device as recited in claim 7 and further including:

means responsive to selected bits in the computer access channel for generating a masking and unmasking signal, and gate means interposed with said interrupt signal and actuated by the masking and unmasking signal for respectively inhibiting and enabling the interrupt signal from passing to the computer.

12. The device as recited in claim 7 and further including:

means synchronized to an AC line frequency for generating a plurality of line synchronized pulses, said line synchronized pulses being coupled to the analog-to-digital converter for initiating conversions thereby.

13. The device as recited in claim 12 and further including:

means responsive to selected bits in the computer access channel for producing an initiate conversion signal and applying said last-mentioned signal to the analog converter for causing computer initiated conversions thereby.

14. The device as recited in claim 7 wherein one of said feature adapters includes:

a digital output producing absolute time indicator selectively coupled to the computer access channel, a source of clock pulses, a presettable counter driven by the source of clock pulses and producing a periodic output signal corresponding to a clock initiated interrupt signal, and means responsive to selected bits in the computer access channel for presetting a count in said counter and correspondingly varying the interval between said periodically occurring clock initiated interrupt signals.

15. The device as recited in claim 16 wherein said masking and unmasking signal generating means includes:

means responsive to selected bits of the computer access channel for decoding a mask command signal, means responsive to selected bits of the computer access channel for decoding a feature adapter signal representative of the group of data lines coupled to external devices causing the interrupt signal, and gating means enabled by the feature adapter signal and responsive to the mask command signal for selectively inhibiting and enabling the interrupt signal with said masking and unmasking signal. An expander for a digital computer real tiMe access channel for real time communication with a plurality of devices located external to the computer comprising;

feature adapters each composed of a group of data lines coupled to external devices and control gates for selectively interconnecting groups of data lines to the computer real time access channel, controller means for directing the flow of data between the computer access channel and said feature adapter groups of data lines, with said controller means including;

means responsive to a signal generated from an external device coupled to said group of data lines for generating a computer interrupt signal, means responsive to selected bits of the computer real time access channel for decoding a mask command signal, means responsive to selected bits of the real time computer access channel for decoding a feature adapter signal representative of the group of feature adapter data lines coupled to the external device initiating the computer interrupt signal, gating means enabled by the feature adapter signal and responsive to the mask command signal for selectively inhibiting and enabling the interrupt signal initiated by said external device.

16. The device as recited in claim 15 wherein said gating means further includes:

first AND gate means responsive to said selected bits used to generate the masking and unmasking signal and enabled by said mask command signal for generating said masking and unmasking signal, and second AND gate means coupled to said masking and unmasking signal and enabled by said feature adapter signal for respectively inhibiting and enabling the interrupt signal.

17. An expander for a digital computer real time access channel for real time communication with a plurality of devices located external to the computer, comprising:

a plurality of feature adapters with selected feature adapters composed of a plurality of channels and control gates for selectively interconnecting the channels to the computer access channel, with feature adapters coupled to the computer access channel to receive data therefrom and transmit data thereto as desired and with external devices coupled to selected feature adapters and channels for communication with the computer through the computer access channel, means responsive to a selected group of bits in the computer access channel for decoding a plurality of identifying feature adapter signals and identifying channel signals, means responsive to a selected group of bits from the computer access channel for decoding control function signals respectively representative of a first interrupt response inquiry and a second interrupt response inquiry from the computer, means associated with each feature adapter and actuated by an external device for generating an interrupt signal to the computer, storing means associated with each feature adapter for storing the interrupt signals from the several devices, means responsive to the first decoded interrupt response inquiry signal for generating a signal indicative of the feature adapter causing the interrupt, means associated with each feature adapter and responsive to the second decoded interrupt response inquiry signal for sensing the stored interrupt signal and generating a signal to identify the channel connected device causing the interrupt, and means responsive to a decoded channel signal corresponding to the identified channel for clearing said storage means.

18. The device as recited in claim 17 wherein said clearing means further comprises:

a first gate means responsive to a selected bit in the computer access channel and actuated by the second interrupt response inquiry signal for generating a clear interrupt signal, and second gate means enabled by said second interrupt response inquiry signal, the clear interrupt signal and a feature adapter identifying signal corresponding to the feature adapter from where the interrupt signal generated for generating a signal for clearing said storing means.