MEMORY ADDRESSING FAILURE DETECTION

• US 3,599,146 A
• Filed: 04/19/1968
• Issued: 08/10/1971
• Est. Priority Date: 04/19/1968
• Status: Expired due to Term

• Current Assignee: Joseph A. Weisbecker
• Original Assignee: Joseph A. Weisbecker
• Inventors: Weisbecker, Joseph A.
• Application Number:
  US04/722,588
• Time in Patent Office: 1,208 Days
• US Class Current: 714/805
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1032 Simple parity

Abstract

A system for detecting errors in the operation of a random access memory which is particularly useful in memories employing semiconductor decoder elements and semiconductor memory elements. Each word storage location in the memory contains a memory address parity bit for the address of that word storage location. When a word storage location is accessed for readout, the parity bit of the memory address employed is compared with the memory address parity bit stored in the word location. If the bits are different, an error signal is generated.

Claims

1. In a random access memory system having addressable word storage locations, the combination of a source of memory addresses each having an associated memory address parity bit, decoder means utilizing a memory address from said source to address a word storage location in the memory, means operative when writing information into an addressed word storage location to store the associated address parity bit in the addressed word storage location, and means operative when reading information from an addressed word storage location to compare the parity bit of the memory address employed with the parity bit read out from the addressed word location, and to generate an error signal if the bits are different.