BINARY TO TERNARY PROTECTED CODE CONVERTER

• US 3,599,205 A
• Filed: 08/28/1968
• Issued: 08/10/1971
• Est. Priority Date: 09/04/1967
• Status: Expired due to Term

• Current Assignee: Duuren Hendrik Cornelis Anthon, Silva Herman Da
• Original Assignee: Duuren Hendrik Cornelis Anthon, Silva Herman Da
• Inventors: DUUREN HENDRIK CORNELIS ANTHON, SILVA HERMAN DA
• Application Number:
  US04/756,020
• Time in Patent Office: 1,077 Days
• US Class Current: 341/57
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes

Abstract

A first code converter comprising two shift registers, one with a counter, and a logic circuit for converting binary code signals having a specified number of bits into protected code signals preferably having the same number of bits and preferably exhibiting a specified 0-bit/1-bit ratio, and a second code converter comprising a counter, a feedback shift register, and two keying devices for converting the 1-bits for transmission at two levels, such as potentials, amplitudes, or frequencies, different from the level at which the 0-bits are transmitted, to form a ternary code with the number of 1-bits transmitted at one level and the number of 1-bits transmitted at the other level exhibiting a constant ratio.

Claims

1. A device for converting multielement first binary code signals into protected multielement ternary code signals of the same number of elements per signal comprising:

A. a first means for converting said first binary code signals into constant ratio binary code signals of two types of elements, and B. a second means for converting all of the elements of one of said two types of binary elements in each signal into a constant ratio of a second and a third type of elements to form a ternary code signal whose elements are transmitted at three different levels.

2. A device according to claim 1 wherein said first converting means converts a specified number of elements of said first binary code signals into said constant ratio binary code signals of the same number of elements as said ternary code.

3. A device according to claim 1 wherein said first converting means converts a specified number of elements of said first binary code signals into said constant ratio binary code signals of the same number of elements as said first binary code.

4. A device according to claim 1 wherein said first converting means comprises two parallel shift registers each having a plurality of triggers corresponding to the elements of the signals, and logic circuits connected to said triggers.

5. A device according to claim 4 wherein one of said shift registers includes as part thereof a counter circuit.

6. A device according to claim 1 wherein said second converting means comprises a counter circuit for said elements of said one type, a feedback shift register connected to and controlled by said counter circuit, and a pair of keying devices, one of which is connected to and controlled by said feedback shift register, and the other of which is controlled by said first convErting means.

7. A device according to claim 6 wherein said keying devices include contacts which are connected in series.

8. A device according to claim 6 wherein said feedback shift register is shifted by the 1-bits from said first converting means.

9. A device according to claim 1 wherein said first converting means is for a specified number of elements of said first binary code signals, and said second converting means is controlled by the remaining elements of said first binary code signals.

10. A device according to claim 9 wherein said second converting means is controlled by said remaining elements of said first binary code signals.