SEMICONDUCTOR FABRICATION TECHNIQUE AND DEVICES FORMED THEREBY UTILIZING A DOPED METAL CONDUCTOR

• US 3,601,888 A
• Filed: 04/25/1969
• Issued: 08/31/1971
• Est. Priority Date: 04/25/1969
• Status: Expired due to Term

• Current Assignee: Marvin Garfinkel, William E. Engeler
• Original Assignee: Marvin Garfinkel, William E. Engeler
• Inventors: Engeler, William E., Garfinkel, Marvin
• Primary Examiner(s): Campbell, John F.
• Assistant Examiner(s): Tupman, W.
• Application Number:
  US04/819,186
• Time in Patent Office: 858 Days
• Field of Search: 29/578,590 148/188,191
• US Class Current: 438/547
• CPC Class Codes: H01L 21/00 Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/48453 of the interface with the bonding area
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H01L 29/00 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor H01L31/00 - H01L33/00, H10K10/00, H10N take precedence; details other than of semiconductor bodies or of electrodes thereof H01L23/00; devices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12036 PN diode
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10S 148/043 Dual dielectric
• CPC Class Codes: Y10S 148/106 Masks, special

Abstract

Semiconductor devices are produced by utilizing a metallic conductor having conductivity-type determining impurities therein and deposited at selected locations on a surface of the semiconductor body. The deposited metallic conductor not only provides good thermal, mechanical, and electrical contact to the surface of the semiconductor body, but in addition acts as an impurity source for a controlling step of diffusing the conductivity-type determining impurities into the semiconductor body. The semiconductor devices thus fabricated are characterized by having regions doped with conductivity-type determining impurities which are substantially coextensive with juxtaposed metal conductors having conductivity-type determining impurities therein.

Claims

2. The method of claim 1 wherein said activator impurity is diffused from said metallic conductor into said semiconductor surface-adjacent region in a preselected pattern.

3. The method of claim 2 wherein said pattern is formed by forming a film of insulating material over the surface of said semiconductor body, removing portions of said insulating film corresponding to said pattern, and depositing said metallic conductor thereover so as to cause said metallic conductor to contact said major active surface only in said pattern, said insulating film being of sufficient thickness to serve as a diffusion mask for said activator impurity.

4. The method of claim 2 wherein said metallic conductor is deposited directly upon an exposed portion of said active major surface and portions thereof are removed to form said pattern.

5. The method of claim 4 wherein said patterned metallic conductor and said semiconductor body are covered with a stabilizing insulating film prior to diffusion of said activator impurity.

6. The method of claim 3 wherein after diffusion said metallic conductor is selectively partially removed in a second predetermined pattern so as to produce a module wherein selected regions of said metallic conductor remain in electricAl contact with at least one of said conductivity-modified surface-adjacent regions of said semiconductor and are electrically isolated from preselected others of said conductivity-modified surface-adjacent regions of said semiconductor body.

7. The method of claim 4 wherein after diffusion a second pattern is formed from said previously patterned metallic conductor member by selective removal of predetermined portions of the previously patterned metallic conductor.

8. The method of claim 1 wherein first and second conductivity modified activator impurities are simultaneously diffused into said active major surface portion of said semiconductor body.

9. The method of claim 8 wherein said first and second activator impurities are present within the same metallic conductor and are diffused into the same active major surface portion:

a. said first activator impurity having a higher diffusion coefficient than said second activator impurity so as to diffuse more deeply into said semiconductory body and form an asymmetrically conductive junction with the surface-adjacent region of said semiconductor the electrical characteristics of which are dominated by said second slower diffusing activator impurity.

10. The method of claim 9 wherein said semiconductor is selected from the group consisting of germanium and silicon, said metallic conductor is selected from the group consisting of tungsten and molybdenum, and said first and second activator impurities are selected from the group consisting of antimony, phosphors, arsenic, bismuth, aluminum, boron, gallium, and indium.

11. The method of claim 8 wherein said first and second activator impurities are present in different metallic conductor portions and diffuse into different active major surface portions to form different conductivity modified surface-adjacent regions of said semiconductor body.

12. The method of claim 1 wherein said metallic conductor is selected from the group consisting of molybdenum and tungsten.

13. The method of making a low impedance contact to a portion of a semiconductor body having a first concentration of a conductivity-modifying impurity:

a. depositing in contact with a surface portion of said portion of said semiconductor body a metallic conductor having a major constituent which does not melt or form an alloy with said semiconductor at activator diffusion temperatures and having as a minor constituent an impurity activator of said one conductivity type, and heating said body to cause said impurity activator in said metallic conductor to diffuse into said portion of said semiconductor body to enhance the concentration of said one conductivity type inducing activatory impurity in a surface-adjacent region with which said metallic inductor is in electrical contact.

14. The method of claim 9 wherein said asymmetrically conductive function is a PN junction.

15. The method of claim 12 in which said enhanced concentration of one conductivity type activator impurity exceeds 1019 per cubic centimeter of semiconductor and said semiconductor is silicon.

16. The method of claim 1 wherein said said diffusion is carried out at a temperature of greater than 1000* C. and said semiconductor is silicon.