METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED BY SAID METHOD

• US 3,602,982 A
• Filed: 04/17/1968
• Issued: 09/07/1971
• Est. Priority Date: 05/13/1967
• Status: Expired due to Term

• Current Assignee: Else Kooi
• Original Assignee: Else Kooi
• Inventors: Kooi, Else
• Primary Examiner(s): Campbell, John F.
• Assistant Examiner(s): Tupman, W.
• Application Number:
  US04/721,953
• Time in Patent Office: 1,238 Days
• Field of Search: 29/578,577,577IC,576IW,175 317/235 148/187,188
• US Class Current: 438/396
• CPC Class Codes: H01L 21/00 Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/82285 Complementary vertical transistors
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/82005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 24/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/12036 PN diode
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect
• CPC Class Codes: Y10S 148/031 Diffusion at an edge
• CPC Class Codes: Y10S 148/051 Etching
• CPC Class Codes: Y10S 148/085 Isolated-integrated
• CPC Class Codes: Y10S 148/117 Oxidation, selective
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method for making an integrated circuit with circuit elements dielectrically isolated is described. The method involves growing an epitaxial layer on a substrate, masking where desired the epitaxial layer surface against oxidation, and sinking a thermal oxide into the epitaxial layer. A support is then mounted on the epitaxial layer top and the substrate removed, for example, by electrolytic etching. Circuit elements are built into the dielectrically isolated semiconductor regions. The technique allows the provision of connections on both sides of the regions containing circuit elements.

Claims

2. A method as set forth in claim 1 wherein the final body thickness is not more than 5 Mu m. and the masking layer comprises silicon nitride.

3. A method as set forth in claim 1 wherein the insulating support comprises polycrystalline silicon or polyvinylacetate.

4. A method as set forth in claim 1 wherein the substrate is removed by a treatment comprising electrolytical etching.

5. A method as set forth in claim 1 wherein prior to mounting of the body on a support, at least one metal track is provided on the surface of the body containing the silica pattern so as to connect to a circuit element in a silicon regions.

6. A method as set forth in claim 5 wherein subsequent to the material removing step, an opening is made in the silica pattern, a conductor is provided on the side of the body from which material was removed, and the conductor is connected to the metal track through the silica pattern opening.

7. A method as set forth in claim 1 wherein at least one metal track is provided on opposite sides of the final thickness of the silicon body so as to contact circuit elements in the silicon regions and extend over the silica pattern.

8. A method as set forth in claim 7 wherein metal layers are provided on opposite sides of a silicon region to form a capacitor, and the metal tracks are connected to the metal layers.

9. A method as set forth in claim 7 wherein two groups of crossing metal tracks are provided, one on each side of the final body, the crossings being located at the silicon regions.