STABLE DIGITAL FILTER APPARATUS

• US 3,609,568 A
• Filed: 06/08/1970
• Issued: 09/28/1971
• Est. Priority Date: 06/08/1970
• Status: Expired due to Term

• Current Assignee: Leland Brooks Jackson
• Original Assignee: Leland Brooks Jackson
• Inventors: Jackson, Leland Brooks
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US05/044,357
• Time in Patent Office: 477 Days
• Field of Search: 328/165,167,159 235/156
• US Class Current: 708/306
• CPC Class Codes: H03H 17/0461 Quantisation; Rounding; Truncation; Overflow oscillations or limit cycles eliminating measures

Abstract

In a digital filter, arithmetic overflows are detected and their kind (whether positive or negative) determined by logical manipulation of the signs of the numeric quantities entering and leaving each arithmetic component of the filter. If net positive or negative overflow is detected, the final result of the filter operation is replaced by a positive or negative full scale numeric quantity, respectively, thereby preventing instability in the filter and suppressing output signal transients.

Claims

1. A stable digital filter for processing an input signal, comprising:

adder means for developing an output signal proportional to the sum of the applied signals;

delay means for delaying the output signal of said adder means for a predetermined interval of time;

multiplier means for multiplying the output signal of said delay means by a predetermined filter coefficient;

means for applying said multiplied signal and an input signal to said adder means;

overflow detecting means responsive to signal conditions in said adder means and said multipLier means for detecting an arithmetic overflow in said filter; and

stabilizing means responsive to said overflow detecting means for altering said processed signal to stabilize said filter when an arithmetic overflow is indicated by said overflow detecting means.

2. The digital filter of claim 1 wherein said overflow detecting means comprises:

first logic means responsive to the signs of the arithmetic quantities represented by said output signal of said adder means and by the output signal of said multiplier for detecting a logical inconsistency in said signs and for producing output signals indicative of the presence of overflow in said multiplier as indicated by said logical inconsistency.

3. The digital filter of claim 2 wherein said overflow detecting means, further comprises:

second logic means responsive to the signs of the arithmetic quantities represented by said signal applied to said digital filter, by said multiplied signal, and by said output signal of said adder for detecting a logical inconsistency in said signs and for producing output signals indicative of the presence of overflow in said adder as indicated by said logical inconsistency.

4. The digital filter of claim 3 wherein said overflow detecting means further comprises:

third logic means responsive to said output signals of said first and second logic means for producing an output signal indicative of the presence of a net overflow in said filter.

5. The digital filter of claim 4 wherein said stabilizing means comprises:

means responsive to the output signal of said third logic means for substituting for the output signal of said delay means a signal representative of the largest arithmetic quantity within the capacity of said filter.

6. A stable digital filter for processing a two'"'"''"'"'s-complement binary coded applied signal comprising:

at least one recirculating signal processing loop including adder means for adding said applied signal and a recirculated signal, converter means responsive to the output signal of said adder for developing output signals representative of the sign and magnitude of the arithmetic quantity indicated by said adder output signal, first delay means for delaying the output signal of said converter means representative of said magnitude for a predetermined interval of time, second delay means for delaying the output signal of said converter means representative of said sign for said predetermined interval of time, multiplier means for multiplying said delayed magnitude signal by a predetermined coefficient, two'"'"''"'"'s-complementation means responsive to said delayed sign signal for producing an output signal representative of the two'"'"''"'"'s-complement of the arithmetic quantity represented by the output signal of said multiplier, and means for applying the output signal of said two'"'"''"'"'s-complementation means to said adder as said recirculated signal;

overflow detecting means responsive to the signs of said representative signals applied to and produced by said adder and said multiplier for detecting a logical inconsistency in said signs indicative of an overflow condition in said filter; and

stabilizing means responsive to said overflow detecting means for stabilizing said filter.

7. The digital filter of claim 6 wherein said overflow detecting means comprises:

first logic means responsive to said multiplier output signal and to the output signal of said second delay means for producing output signals indicative of the presence and sign of overflow in said multiplier;

second logic means responsive to said applied signal, said recirculated signal, and said adder output signal for producing output signals indicative of the presence and sign of overflow in said adder; and

third logic means responsive to said output signals of said first and second logic means for producing output signals indicative, respectively, of the presence and sign of a net overflow in said filter.

8. The digital filer of claim 7 wherein Said stabilizing means comprises:

means responsive to the output signal of said third logic means indicative of the presence of a net overflow in said digital filter for substituting for the output signal of said first delay means a signal representative of the magnitude of the largest arithmetic quantity within the capacity of said filter; and

means responsive to the output signal of said third logic means indicative of the presence of a net overflow in said digital filter for inhibiting the output signal of said second delay means and for applying the output signal of said third logic means indicative of the sign of said net overflow to said two'"'"''"'"'s-complementation means.

9. The digital filter of claim 7 wherein said first logic means comprises:

first and second logical NAND circuits for developing output signals indicative of a positive or negative overflow, respectively, in said multiplier;

means for applying to said first and second logical NAND circuits that part of said multiplier output signal representing the sign of the arithmetic quantity represented by said output signal;

means for applying to said first logical NAND circuit an inverted replica of the output signal of said second delay means; and

means for applying the output signal of said second delay means to said second logical NAND circuit.

10. The digital filter of claim 9 wherein said second logic means comprises:

third and fourth logical NAND circuits for developing output signals indicative of a positive or negative overflow, respectively, in said adder;

means for applying to said third logical NAND circuit inverted replicas of that part of each of said applied and recirculated signals representing the signs of the arithmetic quantities represented by said signals;

means for applying to said third logic NAND circuit that part of said adder output signal representing the sign of the arithmetic quantity represented by said signal;

means for applying to said fourth logical NAND circuit that part of each of said applied and recirculated signals representing the signs of the arithmetic quantities represented by said signals; and

means for applying to said fourth logical NAND circuit an inverted replica of that part of said adder output signal representing the sign of the arithmetic quantity represented by said signal.

11. The digital filter of claim 10 wherein said third logic means comprises:

a fifth logical NAND circuit responsive to the output signals of said first and third logical NAND circuits for developing an output signal indicative of a positive arithmetic overflow occurring in either of said adder or said multiplier;

a sixth logical NAND circuit responsive to the output signals of said second and fourth logical NAND circuits for developing an output signal indicative of a negative arithmetic overflow occurring in either of said adder or said multiplier;

seventh and eighth logical NAND circuits for developing output signals indicative of net positive or net negative overflow, respectively, in said filter;

means for applying to said seventh logical NAND circuit the output signal of said fifth logical NAND circuit;

means for applying to said seventh logical NAND circuit an inverted replica of the output of said sixth logical NAND circuit;

means for applying to said eighth logical NAND circuit the output signal of said sixth logical NAND circuit;

means for applying to said eighth logical NAND circuit an inverted replica of the output signal of said fifth logical NAND circuit;

a ninth logical NAND circuit for developing an output signal when either a net positive or net negative overflow occurs in said digital filter; and

means for applying the output signals of said seventh and eighth logical NAND circuits to said ninth logical NAND circuit.

12. Apparatus for detecting arithmetic overflow oscillations in a digital filter, said filter including arithmEtic units for operating on signals representative of arithmetic quantities, comprising:

positive and negative overflow detecting logic circuits connected to the input and output leads of each of said arithmetic units wherein a positive or negative arithmetic overflow can occur, each generating an output signal indicative of a logical inconsistency in the sign of the arithmetic quantity generated by said arithmetic unit and the signs of said arithmetic quantities operated upon by said arithmetic unit; and

means responsive to said output signals of said positive and negative overflow detecting logic circuits for producing signals indicative of the presence and polarity of a net positive or a net negative overflow in said digital filter.

13. Apparatus for preventing overflow oscillations in a recursive digital filter, said filter including arithmetic units for operating on signals representative of arithmetic quantities, comprising:

positive and negative overflow detecting logic circuits connected to the input and output leads of each of said arithmetic units wherein a positive or negative arithmetic overflow can occur, each generating an output signal indicative of a logical inconsistency in the sign of the arithmetic quantity generated by said arithmetic unit and the signs of said arithmetic quantities operated upon by said arithmetic unit;

means responsive to said output signals of said positive and negative overflow detecting logic circuits for producing overflow control signals indicative of the presence and polarity of a net positive or a net negative overflow in said digital filter; and

means for substituting for the arithmetic quantity computed by the filter the largest positive or negative arithmetic quantity within the capacity of said digital filter when a net positive or net negative overflow, respectively, is indicated by said overflow control signals.

14. Apparatus for suppressing transients in the arithmetic quantities computed by a digital filter, said filter including arithmetic units for operating on signals representative of arithmetic quantities, comprising:

positive and negative overflow detecting logic circuits connected to the input and output leads of each of said arithmetic units wherein a positive or negative arithmetic overflow can occur, each generating an output signal indicative of a logical inconsistency in the sign of the arithmetic quantity generated by said arithmetic unit and the signs of said arithmetic quantities operated upon by said arithmetic unit;

means responsive to said output signals of said positive and negative overflow detecting logic circuits for producing overflow control signals indicative of the presence and polarity of a net positive or a net negative overflow in said digital filter; and

means for substituting for the arithmetic quantity computed by the filter the largest positive or negative arithmetic quantity within the capacity of said digital filter when a net positive or net negative overflow, respectively, is indicated by said overflow control signals.

15. Apparatus for detecting arithmetic overflow in a digital filter, said filter having arithmetic units including adders and multipliers, comprising:

positive overflow detecting means associated with at least one of said arithmetic units wherein a positive arithmetic overflow may occur, each of said positive overflow detecting means being a logic circuit for producing an output signal when the sign of the numerical quantity leaving said arithmetic unit is logically inconsistent with the presence of applied numerical quantities of positive sign;

negative overflow detecting means associated with at least one of said arithmetic units wherein a negative arithmetic overflow may occur, each of said negative overflow detecting means being a logic circuit for producing an output signal when the sign of the numerical quantity leaving said arithmetic unit is logically inconsistent with the presence of applied numerical quAntities of negative sign;

overall positive overflow detecting means responsive to the output signals of said positive overflow detecting means for producing an output signal when one or more of said positive overflow detecting means indicates a positive overflow; and

overall negative overflow detecting means responsive to the output signals of said negative overflow detecting means for producing an output signal when one or more of said negative overflow detecting means indicates a negative overflow.

16. Apparatus for stabilizing a digital filter, said filter having at least one recirculating signal processing loop including arithmetic units, comprising:

positive overflow detecting means associated with at least one of said arithmetic units wherein a positive arithmetic overflow may occur, each of said positive overflow detecting means being a logic circuit for producing an output signal when the sign of the numerical quantity leaving said arithmetic unit is logically inconsistent with the presence of applied numerical quantities of positive sign;

negative overflow detecting means associated with at least one of said arithmetic units wherein a negative arithmetic overflow may occur, each of said negative overflow detecting means being a logic circuit for producing an output signal when the sign of the numerical quantity leaving said arithmetic unit is logically inconsistent with the presence of applied numerical quantities of negative sign;

overall positive overflow detecting means responsive to the output signals of said positive overflow detecting means for producing an output signal when one or more of said positive overflow detecting means indicates a positive overflow;

overall negative overflow detecting means responsive to the output signals of said negative overflow detecting means for producing an output signal when one or more of said negative overflow detecting means indicates a negative overflow; and

means for altering the signal in said recirculating loop to either a positive or negative full-scale numerical value when either a positive or a negative overflow is solely indicated, respectively, by said overall positive or negative overflow detecting means.

17. Apparatus for suppressing transients in the output signal of a digital filter, said filter having arithmetic units including adders and multipliers, for developing an output signal representative of a numerical quantity comprising:

positive overflow detecting means associated with at least one of said arithmetic units wherein a positive arithmetic overflow may occur, each of said positive overflow detecting mans being a logic circuit for producing an output signal when the sign of the numerical quantity leaving said arithmetic unit is logically inconsistent with the presence of applied numerical quantities of positive sign;

negative overflow detecting means associated with at least one of said arithmetic units wherein a negative arithmetic overflow may occur, each of said negative overflow detecting means being a logic circuit for producing an output signal when the sign of the numerical quantity leaving said arithmetic unit is logically inconsistent with the presence of applied numerical quantities of negative sign;

overall positive overflow detecting means responsive to the output signals of said positive overflow detecting means for producing an output signal when one or more of said positive overflow detecting means indicates a positive overflow, overall negative overflow detecting means responsive to the output signals of said negative overflow detecting means for producing an output signal when one or more of said negative overflow detecting means indicates a negative overflow; and

means for altering said output signal of said digital filter to either a positive or negative full-scale numerical value when either a positive or a negative overflow is solely indicated, respectively, by said overall positive or negative overflow detecting means.