REMOTE METER READING SYSTEM

• US 3,609,727 A
• Filed: 03/17/1969
• Issued: 09/28/1971
• Est. Priority Date: 03/17/1969
• Status: Expired due to Term

• Current Assignee: Richard E. Riebs
• Original Assignee: Richard E. Riebs
• Inventors: Riebs, Richard E.
• Primary Examiner(s): Habecker, Thomas B.
• Application Number:
  US04/807,898
• Time in Patent Office: 925 Days
• Field of Search: 340/204,190,201.1
• US Class Current: 340/870.22
• CPC Class Codes: H03M 1/26 with weighted coding, i.e. the weight given to a digit depends on the position of the digit within the block or code word, e.g. there is a given radix and the weights are powers of this radix
• CPC Class Codes: H04M 11/002 with telemetering systems telemetering in general G08C

Abstract

A position encoder and transmitter for an automatic remote meter reading system having a first oscillator producing a relatively high frequency pulse rate and a second oscillator producing a lower frequency pulse rate for disabling the first oscillator and which is determined by the value of the circuit parameters of the second oscillator. An encoder means varies the value of the circuit parameters in accordance with the position of the meter being read so that the rate of the low frequency pulse rate and the number of interruptions of the high frequency pulse rate during a predetermined interval of time indicates the position of the meter.

Claims

1. In a position encoder and transmitter including first and second relatively movable means respectively having a code means including an array of code elements and a code means including a plurality of formation bit means, the combination comprising first circuit means operable to produce an output quantity and second circuit means associated with the information bit means and the first circuit means, said second circuit means being operative to vary the condition of the first circuit means a different predetermined number of times for each relative position of the code elements and information bit means during a constant interval of time for each of said relative positions whereby the number of times the condition of the first circuit means is varied causes a corresponding variation in said output quantity during said interval of time which represents information from each of the information bit means.

2. The combination according to claim 1 wherein said first circuit means produces a constant frequency output quantity.

3. The combination according to claim 2 wherein said second circuit means includes a circuit operative to produce a low frequency having a pulse repetition rate lower than that of said constant frequency, said second circuit means varying the condition of said first circuit means each time a low frequency pulse is produced.

4. The combination according to claim 3 wherein the pulse repetition rate of said low frequency is variable and is determined by the relative positions of the code elements and information bit means so that the constant frequency output is varied a different number of times for each relative position of the code elements and information bit means.

5. The combination according to claim 3 wherein said second circuit means includes shunt circuit means responsive to a pulse from said circuit for varying the condition of said first circuit means.

6. The combination according to claim 2 wherein each of said information bit means has one condition permitting operation of the second circuit means and another condition inhibiting operation of the seconD circuit means.

7. The combination according to claim 6 wherein the number of times per interval of time the second circuit means disables the first circuit means increases with an increased number of said information bit means in said one condition.

8. The combination according to claim 1 wherein each of said plurality of information bit means has a conductive and a nonconductive condition respectively determined by the relative positions of the code elements and the information bit means, each information bit means inhibiting the operation of the second circuit means when in one of said conditions.

9. The combination according to claim 1 wherein said second circuit means is operative to disable the first circuit means a different predetermined number of times for each relative position of the code elements and information bit means during a constant interval of time for each of said relative positions so that said output quantity is interrupted during said interval of time.

10. The combination according to claim 9 wherein said first circuit means produces a constant frequency output quantity.

11. The combination according to claim 10 wherein said second circuit means includes a circuit operative to produce a low frequency having a pulse repetition rate lower than that of said constant frequency, said second circuit means varying the condition of said first circuit means each time a low frequency pulse is produced.

12. The combination according to claim 11 wherein the pulse repetition rate of said low frequency is variable and is determined by the relative positions of the code elements and information bit means so that the constant frequency output is varied a different number of times for each relative position of the code elements and information bit means.

13. The combination according to claim 12 wherein said second circuit means includes shunt circuit means responsive to a pulse from said circuit for varying the condition of said first circuit means.

14. In a system for the encoding and transmittal of information from one location to another including a position encoder and transmitter having first and second relatively movable means each having a plurality of code means, the combination comprising first generating means operative to produce a high frequency signal and second generating means coupled to the first generating means and said other code means and being operative to produce and apply a low frequency to said first generating means, the repetition rate of said low frequency being determined by the relative positions of each of said plurality of code means, the operation of said first generating means being modified each time a pulse of the low frequency is applied thereto whereby the number of times that the operation of the first generating means is modified during a predetermined time interval is indicative of the relative positions of the two plurality of code means.

15. The combination according to claim 14 wherein one of said code means comprises an array of code elements and the other code means comprises a plurality of bit means, each of said bit means having first and second conditions respectively determined by the position of the bit means relative to a code element, each bit means being effective to increase the repetition rate of the low frequency pulse rate when in said first condition and to decrease the repetition rate of the low frequency pulse rate when in said second condition.

16. The combination according to claim 15 wherein said bit means comprises switching circuit means being conductive and nonconductive when said bit means is respectively in its first and second conditions.

17. The combination according to claim 15 wherein said first generating means includes switch means responsive to each pulse of the low frequency pulse rate to modify the operation of the first generating means.

18. The combination according to claim 17 wherein said first generating means is turned off in response To said switch means and said switch means comprises a transistor operative in response to each pulse of the low frequency pulse rate to turn the first generating means off.

19. The combination according to claim 18 wherein said first generating means comprises a first oscillator circuit including a unijunction transistor and said transistor is in circuit with the unijunction transistor to prevent conducting by the unijunction transistor when a pulse of the low frequency pulse rate is applied to said transistor so that the first oscillator circuit is turned off.

20. The combination according to claim 15 wherein said second generating means comprises a second oscillator circuit in circuit with said plurality of bit means.

21. The combination according to claim 20 wherein said second oscillator circuit includes a second unijunction transistor connected to said plurality of bit means and responsive to said first condition of a bit means to produce an output pulse to the first generating means.

22. The combination according to claim 21 wherein said first generating means comprises a first oscillator circuit including a first unijunction transistor and a transistor in circuit with the first unijunction transistor and said second unijunction transistor, said transistor being operative in response to a pulse from second unijunction transistor to prevent conducting of the first unijunction transistor whereby the first oscillator circuit is turned off during the operation of said transistor.