LOGIC EVALUATOR AND ADAPTIVE RECOGNITION NETWORK

• US 3,613,082 A
• Filed: 06/30/1969
• Issued: 10/12/1971
• Est. Priority Date: 06/30/1969
• Status: Expired due to Term

• Current Assignee: Richard J. Bouchard
• Original Assignee: Richard J. Bouchard
• Inventors: Bouchard, Richard J.
• Primary Examiner(s): Wilbur, Maynard R.
• Assistant Examiner(s): Boudreau, Leo H.
• Application Number:
  US04/837,576
• Time in Patent Office: 834 Days
• Field of Search: 340/172.5,146.2,146.3,147 235/92 (54)/ 235/92 (52)/ 235/92 (10)/
• US Class Current: 382/159
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06V 30/194 References adjustable by an adaptive method, e.g. learning

Abstract

A pattern recognition system employs an addressable memory which stores response data concerning patterns. Each input pattern is presented to the system as a binary number and each such number addresses the memory so that response data is read out of the correspondingly numbered memory address. If the data read out of the memory in response to a particular input pattern is not correct, the data in the memory is changed so that the next time that particular pattern is presented to the system, the correct response data is read out of the memory. Binary numbers corresponding to variants to an input pattern can be shifted around in an input register until they correspond to the input pattern number so that the system will respond to these variants as though they were the original input pattern. An adjustable threshold control enables an input pattern to address the memory so that the desired response data is read out of the memory even though there is a discrepancy between the input pattern number and the memory address containing that data. This provides noise immunity as well as further generalization capability. The invention herein described was made in the course of or under a contract or subcontract thereunder with the Department of the Navy.

Claims

1. A pattern recognition system comprising A. an addressable memory for storing pattern response data, B. means for presenting input patterns to the system each in a coded format, C. means for addressing the memory in accordance with the coded format of the each said input pattern so that response data for each said input pattern can be read out of the memory, D. means for shifting around the coded format of a variant of each said input pattern until the variant format substantially corresponds to an address in the memory so that the system responds to the variant as though it was said input pattern, and E. means for correcting the response data stored in the memory when the data read out of the memory in response to each said input pattern is not the desired one so that when said input pattern is again presented to the system, the desired response data is read out of the memory.

2. an adjusting biasing means, and

3. A pattern recognition system as defined in claim 2 and further including an adjustable threshold control responsive to the output of the comparing means, said threshold control emitting a recognition signal to the memory register and punish control, even though a selected number of corresponding bits of the numbers in said input register and address register do not coincide so that correct response data for a pattern is read into the output register, even though the input pattern actually presented to the system for recognition is distorted.

4. A pattern recognition system comprising A. an addressable memory for storing response data concernIng input patterns, B. an input circulating shift register which stores an input pattern as a binary number for presenting each input pattern to the system in a coded format, C. means including a counter for addressing the memory in accordance with the number of each said input pattern so that response data for each said input pattern can be read out of the memory, D. means for correcting the response data stored in the memory when the data read out of the memory in response to each said input pattern number is not the desired data so that when the input pattern number is again presented to the system, the desired response data is read out of the memory, and E. means for shifting the input pattern number around in the input register so that numbers representing variants of each said input pattern can be translated into the number for that input pattern, whereby the system responds to the variants as though they were that input pattern.

5. A pattern system as defined in claim 4 and further including means for storing the desired response data for each of the variants in the memory so that when any of these variants is again presented to the system, the desired response data is read out of the memory.

6. A pattern recognition system comprising A. an address register for storing binary numbers representing locations in a memory, B. an addressable recirculating memory, including a shift register associated with the address register and arranged to contain data at the address addressed by the address register, C. an input register for storing a binary number representing an input pattern, D. means for comparing the numbers in said address register and said input register, said comparing means emitting a recognition signal when the two numbers coincide, E. an output register responsive to the signals from said comparing means for reading out response data from the correspondingly numbered memory address, and F. a punish control associated with the memory for changing the contents of the correspondingly numbered memory address when the data read into the output register is incorrect, said punish control being arranged to route signals from the comparing means to selected stages of the memory register so that the content thereof is complemented the next time the two numbers coincide.

7. A pattern recognition system comprising A. an addressable memory for storing pattern response data, B. An input register for storing a binary number representing an input pattern, C. means for addressing the memory in accordance with the number contained in the input register so that data at the memory address corresponding to that number is read out of the memory, D. output means responsive to the data read out of the memory, E. means for shifting an input pattern number around the input register so as to create a series of numbers representing variants of the input pattern, and F. said addressing means addressing the memory when a number in the series corresponds to a memory address so that the output means responds to selected input pattern variants.

8. A pattern recognition system as defined in claim 7 and further including means for changing the response data stored in the memory when the response of the output means to a particular input pattern or variant thereof is not the correct response so that when that input pattern or variant thereof is again presented to the system, the output means responds correctly.

9. A pattern recognition system as defined in claim 7 and further including an adjustable noise-immunity control which enables the addressing means to address a memory location whose address is different by a selected number of bits from an input pattern number.

10. A pattern recognition system as defined in claim 9 and further including means for changing the response data stored in the memory when the response of the output means to a particular input pattern or variant thereof is not the correct response so that when that input pattern or variant thereof is again presented to the system, the output means responds correctly.

11. A pattern recognition system comprising A. an addressable recirculating memory for storing response data for input patterns, B. an address register associated with the memory and for storing binary numbers representing locations in the memory, C. an input register for storing a binary number representing an input pattern, D. means for comparing the numbers in said address register and said input register, said comparing means emitting a recognition signal when the two numbers coincide, E. an output register responsive to the signals from said comparing means for reading out response data from the correspondingly numbered memory address, F. a punish control associated with the memory for changing the contents of the correspondingly numbered memory address when the data read into the output register is incorrect, and G. further including means for shifting the binary number around in the input register so as to create a series of new numbers, said comparing means emitting a recognition signal to said output register whenever a number in the series coincides with the number in the address register so that the system is able to recognize a series of input pattern variants.

12. A pattern recognition system as defined in claim 11 wherein each number in the series created by shifting the contents of the input register addresses the memory so that response data for a series of input pattern variants can be stored in the memory.

13. A pattern recognition system for storing response data for input patterns comprising A. an addressable recirculating memory including a shift register, B. an output register connected to receive the contents of the memory register upon receiving command signals, C. display means arranged to respond to the contents of the output register, D. an input register for containing a binary number representing an input pattern, E. a counter arranged to cycle through a count corresponding to the number of addresses in the memory, each count in the counter denoting the address of the response data contained in the memory register at the time of the count, F. means for comparing the numbers contained in the input register and the counter, said comparing means emitting signals which indicate the degree of coincidence between the numbers contained in the input register and counter, G. a threshold control responsive to the output of the comparing means, said threshold control emitting a command signal to the output register upon receipt of signals from the comparing means indicating a selected degree of coincidence, and H. means for adjusting the threshold control so that the operator can vary the degree of coincidence required between the two numbers being compared before the comparing means emits a command signal, whereby the correct response data for a particular pattern is loaded into the output register and displayed by the display means, even though the input pattern being examined is a distortion of that particular pattern.

14. A pattern recognition system as defined in claim 13 and further including a punish control arranged to route command signals from the threshold control to selected stages of the memory register when the data displayed by the display means in response to a particular input pattern number in the input register is incorrect so as to change the data in the memory register so that the next time that particular input pattern number is contained in the input register, the desired response data will be loaded into the output register and displayed by the display means.

15. A pattern recognition system as defined in claim 14 A. wherein the input register is a circulating register, and B. further including means for shifting an inpuT pattern number around in the input register so as to create a series of binary numbers corresponding to variants of the input pattern.

16. A pattern recognition system as defined in claim 15 and further including means for storing in the memory response data for each pattern number in the series created by shifting the contents of the input register so that the next time input patterns corresponding to any of these numbers is presented to the system, the display means displays the correct response for that pattern.

17. A pattern recognition system as defined in claim 16 A. wherein the comparing means comprises a set of gates, each gate responding to the contents of corresponding stages of the input register and counter, and B. the threshold control comprises

18. A pattern recognition system comprising A. an addressable recirculating memory for storing response data for input patterns, B. an address register associated with the memory, and for storing binary numbers representing locations in the memory, C. an input register for storing a binary number representing an input pattern, D. means for comparing the numbers in said address register and said input register, said comparing means including a series of gates, each being connected to respond to the content of corresponding different stages of the input and address registers and said comparing means emitting a recognition signal when the two numbers coincide, E. an output register responsive to the signals from said comparing means for reading out response data from the correspondingly numbered memory address, F. a punish control associated with the memory for changing the contents of the correspondingly numbered memory address when the data read into the output register is incorrect, and G. an adjustable threshold control responsive to the output of the comparing means, said threshold control emitting a recognition signal to the memory register and punish control, even through a selected number of corresponding bits of the numbers in said input register and address register do not coincide so that correct response data for a pattern is read into the output register even through the input pattern actually presented to the system for recognition is distorted, said threshold control comprising