CIRCUIT FOR KEEPING THE FREQUENCY OF AN INVERTER SYNCHRONIZED WITH THE FREQUENCY OF ANOTHER SOURCE

• US 3,614,461 A
• Filed: 02/02/1970
• Issued: 10/19/1971
• Est. Priority Date: 08/11/1969
• Status: Expired due to Term

• Current Assignee: Dennis F. Williamson, Gordon W. Speer
• Original Assignee: Dennis F. Williamson, Gordon W. Speer
• Inventors: Speer, Gordon W., Williamson, Dennis F.
• Primary Examiner(s): Beha, Jr., William H.
• Application Number:
  US05/007,546
• Time in Patent Office: 624 Days
• Field of Search: 307/45,46,64,66,80,87 324/83A,87 321/4
• US Class Current: 307/64
• CPC Class Codes: H02P 9/42 to obtain desired frequency without varying speed of the generator

Abstract

In an uninterruptible power supply comprising a normal source of alternating voltage, a rectifier/battery charger, a battery, and a static inverter, the inverter is kept in synchronism with the normal source by controlling its frequency in accordance with an error signal which is representative in magnitude and polarity of any deviation in phase between the output voltage of the inverter and the voltage of the normal source.

Claims

1. In combination:

a. a set of electric power feeder lines adapted to be connected to a predetermined source of alternating voltage;

b. a set of electric power load lines;

c. an inverter having a DC input side and an AC output side, said output side being normally connected to said load lines to supply the same with alternating voltage;

d. means for interconnecting said feeder lines and the input side of said inverter;

e. means associated with said inverter for controlling the frequency of the alternating voltage Which is thereby supplied to said load lines;

f. a synchronizing circuit coupled to both of said sets of lines for producing an error signal whose magnitude and polarity depend on the deviation in phase of the voltage supplied by said inverter from the voltage supplied by said predetermined source; and

g. means for applying said error signal to said control means which consequently corrects the inverter frequency so as to minimize any phase deviation between said voltages.

2. The combination of claim 1 wherein said synchronizing circuit comprises:

filtering means having input and output terminals;

means coupled to a predetermined one of said sets of lines for deriving an input signal representing the alternating voltage on those lines;

AC switch means for applying said input signal to the input terminals of said filtering means during periodic intervals when said switch means is '"'"''"'"''"'"''"'"'on'"'"''"'"''"'"''"'"'; and

means energized by the alternating voltage on the other set of lines for deriving therefrom a representative reference signal and for gating said switch means '"'"''"'"''"'"''"'"'on'"'"''"'"''"'"''"'"' during alternate half-cycles of said reference signal;

said signal deriving means being so connected and arranged that said input and reference signals are apart in phase by approximately 90 electrical degrees whenever there is no phase deviation between said voltages;

said error signal being the average voltage produced at the output terminals of said filtering means.

3. The combination of claim 2 wherein said filtering means is a capacitance-reactance network.

4. The combination of claim 2 wherein said predetermined one set of lines comprises said feeder lines and said other set comprises said load lines.

5. The combination of claim 2 wherein said AC switch means comprises a first bidirectional transistor switching circuit arranged to apply the input signal directly to said filtering means and a second bidirectional transistor switching circuit arranged to apply the input signal with inverted polarity to said filtering means;

and wherein said gating means is arranged to gate the transistors in said first circuit '"'"''"'"''"'"''"'"'on'"'"''"'"''"'"''"'"' and those in said second circuit '"'"''"'"''"'"''"'"'off'"'"''"'"''"'"''"'"' during each positive half-cycle of said reference signal and to gate the transistors in said second circuit '"'"''"'"''"'"''"'"'on'"'"''"'"''"'"''"'"' and those in said first circuit '"'"''"'"''"'"''"'"'off'"'"''"'"''"'"''"'"' during each negative half-cycle of said reference signal.

6. The combination of claim 5 wherein said input signal deriving means comprises a transformer having a primary connected to said feeder lines and a center tapped secondary, said first and second switching circuits being respectively connected between a common input terminal of said filtering means and opposite ends of said secondary, and another input terminal of said filtering means being directly connected to said center tap.

7. The combination of claim 5 wherein said reference signal is a substantially square wave alternating voltage of constant amplitude comprising positive and negative gating pulses for said first and second switching circuits respectively.

8. The combination of claim 7 wherein said gating means comprises a transformer having a primary energized by said reference signal and having two secondaries, one for each switching circuit of the AC switch means connected in the circuit for gating the transistors.