READ-ONLY MEMORY CIRCUIT

• US 3,614,750 A
• Filed: 07/15/1969
• Issued: 10/19/1971
• Est. Priority Date: 07/15/1969
• Status: Expired due to Term

• Current Assignee: John L. Janning
• Original Assignee: John L. Janning
• Inventors: Janning, John L.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US04/841,760
• Time in Patent Office: 826 Days
• Field of Search: 340/173,17 307/238,279
• US Class Current: 365/104
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H01L 29/00 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor H01L31/00 - H01L33/00, H10K10/00, H10N take precedence; details other than of semiconductor bodies or of electrodes thereof H01L23/00; devices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

The present invention relates to a read-only memory card comprising a coded array of dielectric coated gate electrodes mounted on a nonconductive substrate. The invention also relates to a read-only memory card reader for reading said read-only memory card comprising source electrode-semiconductor materialdrain electrode elements on a nonconductive substrate. Fieldeffect transistors are formed when the read-only memory card is placed on the read-only memory card reader. The field-effect transistors are probed by applying a gate voltage to the coded array of dielectric coated gate electrodes of the read-only memory card and applying a source-drain voltage to each element of the read-only memory card reader. The field-effect transistors, only, will conduct a source-drain current. A sourcedrain current, which passes through the completed field-effect transistors, is sensed, in order to read the information in the read-only memory card.

Claims

2. A read-only memory card reader to be used in conjunction with a read-only memory card, so as to form a storage unit of bits of information, comprising:

a. a second nonconductive supporting substrate, b. a matrix of source electrodes attachably disposed on said second nonconductive supporting substrate, c. a matrix of drain electrodes attachably disposed on said second nonconductive supporting substrate in a close alternating arrangement with said source electrodes, and d. semiconductor material attachably disposed between said source electrodes and said adjacent drain electrodes of the matrix of source and drain electrodes, so as to form a matrix of source electrode-semiconductor material-drain electrode elements against which a coded array of gate electrodes may lie in insulative contact.

3. A read-only memory circuit for reading a read-only memory card with a read-only memory card reader, comprising:

a. a read-only memory card reader having a second nonconductive supporting substrate, a matrix of source electrodes attachably disposed on said second nonconductive supporting substrate, a matrix of drain electrodes attachably disposed on said second nonconductive supporting substrate in close alternating arrangement with said source electrodes, and semiconductor material attachably disposed between said source electrodes and said adjacent drain electrodes;

b. a read-only memory card in register with said read-only memory card reader having a first nonconductive supporting substrate, a coded array of gate electrodes attachably disposed on said first nonconductive supporting substrate, and a dielectric coating covering said coded array of gate electrodes in contact with said matrix of thin semiconductor material, the gate electrodes being in registration with said matrix of thin semiconductor material;

c. a set of first copper conductors, each connecting a row of the matrix of source electrodes;

d. a set of second copper conductors, each connecting a column of the matrix of drain electrodes;

e. a set of source electrode switches, each connected to a first copper conductor;

f. a set of drain electrode switches, each connected to a second copper conductor;

g. a set of ammeters, each connected to a source electrode switch;

h. a source-drain voltage battery connected between the connected ammeters and the connected drain electrode switches; and

i. a gate voltage battery connected between the connected ammeters and the coded array of gate electrodes so that a source-drain current will flow between a source electrode and a drain electrode when its corresponding source electrode switch and drain electrode switch are closed if a gate electrode exists thereabove and through the corresponding ammeter connected to said source electrode switch.

4. A method of reading a read-only memory card having a first nonconductive supporting substrate, a coded array of gate electrodes attachably disposed on said first nonconductive supporting substrate, and a dielectric coating covering said coded array of gate electrodes, by means of a read-only memory card reader having a second nonconductive supporting substrate, a matrix of source electrodes attachably disposed on said nonconductive supporting substrate, a matrix of drain electrodes attachably disposed on said second nonconductive supporting substrate in a close alternating arrangement with said source electrodes, and semiconductor material attachably disposed between said source electrodes and said adjacent drain electrodes of the matrix of source and drain electrodes, comprising:

a. placing the dielectric coating of the read-only memory card against the semiconductor material;

b. registering the coded array of gate electrodes with the semiconductor mate material between source and drain electrodes;

c. applying a gate voltage to the coded array of gate electrodes with respect to the array of source electrodes; and

d. applying a source-drain voltage between each source electrode and adjacent drain electrode, so as to pass a source-drain current if a gate electrode exists thereabove, so as to sense for the presence or absence of gate electrodes within the coded array of gate electrodes.