TABLE LOOK-UP MODULATOR

• US 3,617,941 A
• Filed: 08/03/1970
• Issued: 11/02/1971
• Est. Priority Date: 08/03/1970
• Status: Expired due to Term

• Current Assignee: Joseph Delellis Jr
• Original Assignee: Joseph Delellis Jr
• Inventors: DeLellis, Joseph Jr.
• Primary Examiner(s): Brody, Alfred L.
• Application Number:
  US05/060,274
• Time in Patent Office: 456 Days
• Field of Search: 332/16R,16T,9R,9T,11 325/30,163 178/66,67,88
• US Class Current: 332/103
• CPC Class Codes: H04L 27/2092 with digital generation of the modulated carrier (does not include the modulation of a digitally generated carrier)

Abstract

A table look-up modulator employs a phase control unit connected to a modulating means to generate in digital form a first and second plurality of tones at a predetermined baud rate. The phase of each tone is determined by a separate pair of input bits to be transmitted. During a first time interval (equal to the reciprocal of half the sampling rate), the second plurality of tones are heterodyned and combined with the first plurality of tones to generate a composite signal at one-half the sampling rate. During a second time interval, a signal representing an interpolated value of the second plurality of tones is generated at one-half the sampling rate. The combination of the composite signal generated during the first time interval and the signal representing the interpolated value generated during the second time interval is directed from the table look-up modulator at the sampling rate.

Claims

1. A table look-up modulator comprising:

first control means operative to generate a modulation control signal in response to an input data sequence;

table look-up means coupled to said control means and being operative in response to the control signal to generate a first and second plurality of selected frequency signals at a first predetermined rate;

heterodyning means coupled to said table look-up means and being operative to multiply each of said second plurality of selected frequency signals by a predetermined signal to generate a third plurality of selected frequency signals;

first summation means coupled to said table look-up means and said heterodyning means and being operative to add said first plurality of selected frequency signals to said third plurality of selected frequency signals to form a composite signal at the first predetermined rate;

interpolating means having an input connection coupled to said table look-up means and an output connection coupled to said heterodyning means and being operative to generate an interpolated value of a set of said second plurality of selected frequency signals selected from two data intervals;

said heterodyning means being operative to multiply each of the interpolated signals by a predetermined signal to generate a fourth plurality of selected frequency signals having the interpolated value; and

second control means coupled to said table look-up means and said interpolating means and being operative in response to a signal at a second predetermined rate applied thereto to activate alternately said table look-up means and said interpolating means, whereby said composite signal and said fourth plurality of selected frequency signals having the interpolated value represent a modulated form of the input data sequence at a third predetermined rate.

2. A modulator device according to claim 1 wherein said table look-up means includes:

a clock having a first input coupled to said second control means, a second input connection and an output connection and being operative in response to a signal from said second control means to generate a series of clock pulses at its output connection and being operative in response to a signal at its second input connection to inhibit the generation of said series of clock pulses;

first counter means having an input connection connected to the output connection of said clock, a single output connection and a first plurality of output connections, a first predetermined one of which is connected to the second input connection of said clock, said first counter means being operative in response to said clock pulses to generate at its single output connection a series of signals representing a series of numbers and to generate a control pulse at one of said plurality of output connections each time said first counter means generates one of said series of signal;

function storage means having input and output connections and being operative to store a predetermined number of sample signals representing one cycle of a predetermined mathematical function;

address means having a first input connection coupled to said first control means, a second input connection coupled to the single output connection of said first counter means and an output connection coupled to said function storage means and being operative in response to control signals from said first control means and the series of signals from first counter means to address predetermined samples of signals stored in said function storage means to generate a series of tone signals; and

accumulator means coupled to the output connection of said function storage means and to a first predetermined one and a second predetermined one of said plurality of output connections of said first counter means and being operative in response to a signal from said first predetermined one of said plurality of output connections to accumulate a sum of a first predetermined number of said tone signals and being operative in response to a signal from said second predetermined one of said plurality of output connections to accumulate a Sum of a second predetermined number of said tone signals.

3. A modulator device according to claim 2 wherein said heterodyning means includes:

second counter means having a first input connection coupled to said second control means, a second input connection coupled to said first counter means and an output connection, and being operative in response to each signal at said first and second input connections to increment a counter output signal;

cosine storage means having an input connection connected to said second counter means and being operative to store a predetermined number of signals representing one cycle of a cosine function, said cosine storage means being operative in response to each output signal from said second counter means to exit one of said predetermined number of signals representing the cosine function;

first multiplier means having a first and second input connection coupled to said cosine storage means and said accumulator means, respectively, and being operative to multiply the accumulated sum of a second predetermined number of tone signals by the output signals of said cosine storage means to form a product signal representing the heterodyned version of said tone signals; and

second multiplier means having a first and second input connection, respectively, coupled to said cosine storage means and to the output connection of said interpolating means and being operative to multiply the output signals from said interpolating means by the output signals of said cosine storage means to form a product signal representing the heterodyned version of the output signals of said interpolating means.

4. A modulator device according to claim 3 wherein said interpolating means includes:

first and second storage means each having an input connection coupled to said accumulator means and an output connection, said first storage means being operative to store an accumulated sum of a second predetermined number of tone signals from a previous time interval, said second storage means being operative to store an accumulated sum of a second predetermined number of tone signals from a subsequent time interval;

an adder circuit coupled to said first and second storage means and being operative to add the signals stored in said first and second storage means; and

a divider circuit having an input connection coupled to said adder circuit ans an output connection coupled to said second multiplier circuit of said heterodyning means and being operative to divide the output signal of said adder circuit by a predetermined factor to form an output signal representing an interpolated value of the signals stored in said first and second storage means.