APPARATUS PROCESSING PULSE NUMBERS FOR USE IN A PID DIGITAL CONTROL SYSTEM

• US 3,621,357 A
• Filed: 08/28/1969
• Issued: 11/16/1971
• Est. Priority Date: 10/25/1968
• Status: Expired due to Term

• Current Assignee: Moritada Kubo, T., William Miles, Yukiharu Takahashi
• Original Assignee: Moritada Kubo, T., William Miles, Yukiharu Takahashi
• Inventors: Takahashi, Yukiharu, Kubo, Moritada, T., William Miles
• Primary Examiner(s): T. E. Lynch
• Application Number:
  US04/853,813
• Time in Patent Office: 810 Days
• Field of Search: 318/600,603
• US Class Current: 318/600
• CPC Class Codes: H03K 5/00 Manipulating of pulses not covered by one of the other main groups of this subclass circuits with regenerative action H03K3/00, H03K4/00; by the use of non-linear magnetic or dielectric devices H03K3/45
• CPC Class Codes: H03K 5/01 Shaping pulses discrimination against noise or interference H03K5/125

Abstract

Apparatus for obtaining the proportional difference between two pulse trains by feeding input pulses of the two pulse trains to an anticoincidence circuit, which blocks the passage of only coincidence inputs the outputs from which are supplied to a combining circuit including a flip-flop circuit and a pair of AND gate circuits, thereby canceling the first of the alternately reached pulses in two trains to obtain the rest of the pulses. By combining the apparatus with a step motor and delay circuits the integral difference and differential difference may be obtained.

Claims

1. Apparatus for processing pulse signals to obtain signals corresponding to the frequency difference between two pulse trains comprising a detector means including:

an anticoincidence circuit eliminating only coincident input pulses between first and second input pulse trains and producing first and second output pulse trains respectively consisting of the remainder of the pulses of the corresponding input pulse trains other than said eliminated coincident pulses;

a flip-flop circuit set by a falling portion of the pulses in said first output pulse train and reset by a falling portion of the pulses in said second output pulse train to produce respective outputs F and F;

a first gate circuit receiving said first output pulse train and said output F and producing the difference of the pulse frequency of said first input pulse train from the pulse frequency of said second input pulse train; and

a second gate circuit receiving said second output pulse train and said output F and producing the difference of the pulse frequency of said second input pulse train from the pulse frequency of said first input pulse train;

the outputs of said first and second gate circuits representing the difference between the frequencies of said first and second input pulse trains.

2. Apparatus as claimed in claim 1, comprising a gain regulator coupled to the outputs of said first and second gate circuits for regulating the gain of the output pulse trains from said first and second gate circuits.

3. Apparatus as claimed in claim 2, wherein said gain regulator comprises flip-flop circuits respectively connected to the outputs of said first and second gate circuits, pulse generators, AND gates each receiving outputs from the corresponding ones of said regulator flip-flops and said pulse generators, frequency dividers each receiving an output from a corresponding one of said AND gates, and preset counters each receiving an output from a corresponding one of said AND gates and providing an output to the reset terminal of a corresponding one of said regulator flip-flop circuits.

4. Apparatus as claimed in claim 1, comprising a step motor receiving the outputs from said gate circuits respectively as clockwise and counterclockwise signals for converting the integral of the difference between the pulse frequencies of said first and second input pulse trains into a corresponding angle of rotation.

5. Apparatus as claimed in claim 1, comprising a step motor for converting the difference between the pulse frequencies of said first and second input pulse trains into an integral difference corresponding to an angle of rotation, a controlled system controlled by said step motor and a pulse converter converting an output from said controlled system into said second input pulse train.

6. Apparatus as claimed in claim 1, comprising means for controlling the gain of the output pulse trains from said first and second gate circuits, a step motor receiving the outputs from said gain control means, a controlled system controlled by said step motor, and a pulse converter converting output from said controlled system into said second input pulse trains.

7. Apparatus as claimed in claim 1 comprising delay means coupled to receive said first input pulse train, the output of said delay means comprising said second input pulse train, the outputs of said gate circuits being a function of a differential value of the pulse number density of said first pulse train.

8. Apparatus as claimed in claim 1 comprising:

second and third detector means, the outputs from the first and second gate circuits of said first detector means being coupled to a first input of said second and third detector means, respectively;

second and third delay means, said second delay means coupling the output from said first gate circuit of said first detector means to the other input of said second detector means and said third delay means coupling the output of said second gate circuit of said first detector means to the other input of said third detector means;

at least one gate circuit coupled to the output of at least one of said second and third detector means for deriving plus and/or minus, differential values of pulse number densities.

9. Apparatus as claimed in claim 1 wherein said first and second gate circuits are AND circuits, the output of said first gate circuit representing a plus difference and the output of said second gate circuit representing a minus difference between the frequencies of said first and second input pulse trains.

10. Apparatus as claimed in claim 8 comprising a first OR gate coupled to the first output of said first detector means and to the second output of said second detector means, and a second OR gate coupled to the second output of said first detector means and to the first output of said second detector means.